Lead Embedded CPU PPA Architect

Job Title

Lead Embedded CPU PPA Architect

Role Summary

Lead the power, performance and area (PPA) architecture effort for embedded CPU core and cache complexes to ensure products meet performance targets within power, thermal, platform and reliability constraints. This is a technical leadership role that drives alignment between CPU IP teams, Embedded product teams, package/platform, power/thermal engineering, and firmware/BIOS across product definition and program milestones.

Experience Level

Senior — typically 7–10 years of relevant experience, with demonstrated cross-functional technical leadership and ownership of end-to-end workstreams.

Responsibilities

Lead and coordinate technical activities to deliver PPA targets across product definition and program readiness:

• Translate product usage models, workloads and reliability requirements into IP performance, power and thermal constraints.
• Drive alignment on power delivery architecture, PDN/PI margins, and packaging/platform implications with SIPI, packaging and platform partners.
• Define and validate thermal operating margins and thermal management requirements with package and platform teams.
• Establish power targets and bounding boxes (BBox) for program reviews and provide data-backed tradeoffs (power vs. performance vs. platform cost).
• Maintain a structured open-items process for risks, dependencies and required decisions; drive timely closure and represent the workstream in program forums.
• Lead technical reviews across SoC architecture, physical implementation, package and platform definition.
• Partner closely with pre-silicon power & performance modeling teams to align assumptions, rail targets and use-case definitions; consume model outputs to set architecture budgets and targets.
• Collaborate with firmware/BIOS, validation, and platform teams to ensure multi-dimensional alignment of reliability, power delivery and performance constraints.

Requirements

Must-have:

• Proven technical leader with experience driving cross-functional alignment across architecture, physical design, firmware/BIOS, packaging and platform.
• Strong understanding of SoC architecture and low-power designs: rails, low-power modes, performance states and power/use-case budgeting.
• Working knowledge of PDN and PI principles (IR drop, droop, impedance, decaps, noise budgeting) and ability to drive closure with packaging/platform partners.
• Familiarity with device and system reliability requirements and thermal management algorithms.
• Experience collaborating with pre-silicon power & performance modeling teams and translating model outputs into architectural constraints and targets.
• Experience driving program milestone readiness and managing technical workstreams to review-ready state.

Nice-to-have:

• Experience with CPU core/cache IP, package design, SIPI and platform validation.
• Background in embedded product requirements and operating-condition definitions.
• Experience with thermal modeling tools and packaging-level tradeoffs.

Education Requirements

BS or MS in Electrical Engineering or Computer Engineering (or equivalent). The role expects ~7–10 years of relevant experience; equivalent practical experience may be accepted in lieu of the listed degrees.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.