Lead Digital Verification Engineer

Job Title

Lead Digital Verification Engineer

Role Summary

Lead engineer responsible for verification of digital RTL and development of reusable verification components and environments for high-performance physical IP. Works within a small, focused IP verification team and collaborates with design, project management, and cross-site engineering teams.

Primary mission is to plan and execute verification flows to achieve functional and code coverage closure and deliver high-quality IP on schedule.

Experience Level

Senior / Lead. Years of experience: Not specified.

Responsibilities

The role focuses on planning, implementing, and executing digital verification activities and verification infrastructure.

• Verify digital RTL and ensure functional correctness for IP blocks.
• Design, implement, and maintain reusable verification components and UVM environments.
• Develop and execute test plans; drive metric-driven verification to closure.
• Define and implement functional coverage and assertion checks; close functional and code coverage gaps.
• Develop and improve verification flows and automation to increase productivity.
• Collaborate with RTL designers, analog/mixed-signal teams, physical design, and project management across multiple locations.
• Report progress, risks, and status to technical leads and project managers.
• Work onsite (Montreal) full time; travel as required (approximately 5% or less).

Requirements

Must-have skills and competencies followed by preferred skills.

• Must-have: Strong understanding of verification architecture and methodologies, including metric-driven verification and UVM concepts.
• Must-have: Familiarity with SystemVerilog Assertions (SVA) and digital design flow; experience with RTL verification and debug.
• Must-have: Ability to develop verification environments, testbenches, and verification IP; good problem-solving and communication skills (English required).
• Nice-to-have: Hands-on experience coding in SystemVerilog UVM.
• Nice-to-have: Experience with scripting languages such as Python, Perl, Ruby, sed, or awk to support automation.
• Nice-to-have: Exposure to standard protocols (PCIe, USB, SATA, Ethernet, DisplayPort, HDMI), formal verification technologies, mixed-signal verification, Cadence tools, and low-power verification (CPF/UPF).

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field is required. A Master of Science in a related field is preferred. Documentation of equivalent academic credentials or relevant experience was not specified.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.