Lead Digital Verification Engineer

Job Title

Lead Digital Verification Engineer

Role Summary

Lead the functional verification strategy and execution for complex SoC/IP designs from specification through tapeout. You will define methodology standards, own verification sign-off criteria, and build and mentor a verification team within a growing hardware engineering organization.

The role combines deep technical expertise in modern verification methodologies (UVM, SystemVerilog, constraint-random, assertions) with program-level leadership to deliver verified silicon on schedule.

Experience Level

Senior — typically 10+ years in ASIC/SoC design verification with at least 3 years in a lead role owning verification strategy, sign-off, and team execution.

Responsibilities

Lead verification strategy, architecture, execution, and sign-off across block, subsystem, and full-chip levels.

• Define end-to-end verification strategy aligned to tapeout milestones.
• Author and review verification plans mapping specs to stimulus, coverage, and sign-off criteria.
• Architect scalable UVM testbenches: agents, scoreboards, reference models, and coverage monitors.
• Drive constrained-random stimulus and compiler-driven testing to exercise protocol interactions and corner cases.
• Implement and validate SystemVerilog Assertions for protocol compliance and design invariants.
• Lead full-chip verification (boot, interrupts, DMA, reset, multi-block interactions) and CDC/RDC coordination.
• Debug complex multi-block simulation failures and manage the bug lifecycle through cross-functional resolution.
• Manage regression framework, CI/CD integration, and simulation-to-emulation handoff.
• Represent verification readiness in tapeout sign-off reviews and mentor verification engineers.

Requirements

Key technical and leadership requirements. Education details are listed separately below.

• 10+ years of ASIC/SoC verification experience; minimum 3 years in a lead role owning verification strategy and sign-off.
• Deep expertise in UVM-based testbench architecture and constrained-random methodology.
• Advanced SystemVerilog verification skills (classes, constraints, functional coverage, SVA, interfaces, packages).
• Proven track record driving functional and code coverage to tapeout sign-off on complex SoC designs.
• Strong debug skills for multi-block, protocol, and timing-dependent failures.
• Solid understanding of SoC building blocks (processors such as ARM/RISC-V, AMBA AXI/ACE/CHI, memory controllers, DMA, interrupts, peripherals).
• Scripting and automation proficiency (Python, Perl, or Tcl) for test automation, log analysis, and coverage post-processing.
• Effective communicator of verification status, risks, and trade-offs to technical and program leadership.
• Experience integrating verification flows with emulation, gate-level simulation, and CI/CD pipelines.

Education Requirements

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: Efficient Computer

Headquarters: Austin, TX, USA

Developer of ultra-low-power general-purpose processors using patented technology that can consume up to 100x less energy than comparable ultra-low-power processors. Their programmable platform supports standard high-level languages and AI/ML frameworks to enable long-lived, battery-powered edge devices and energy-efficient SoCs for IoT and edge AI applications.