Lead DFT Engineer

Job Title

Lead DFT Engineer

Role Summary

As the Design for Test (DFT) Lead, you will define and execute DFT strategy for complex SoCs targeting edge-to-cloud computing, ensuring manufacturability, testability, and field reliability.

You will lead DFT architecture and implementation, drive post-silicon bring-up on ATE, and coordinate with design, physical design, and yield teams to meet coverage, area, power, and timing constraints. Salary range: $200,000–$250,000 per year.

Experience Level

Senior — 12+ years in DFT, including at least 2 years in a leadership or principal role.

Responsibilities

Primary responsibilities include defining test architecture, implementing DFT flows, and leading post-silicon validation.

• Define and implement end-to-end DFT architecture for complex SoCs (Hierarchical DFT, scan compression, boundary scan, MBIST).
• Develop In-System Test (IST) and power-on self-test (POST) strategies for edge deployments.
• Oversee scan insertion and ATPG (stuck-at, transition, path delay); supervise Memory/Logic BIST implementation and repair flows.
• Collaborate with Design, Physical Design, and Yield teams to maximize test coverage while minimizing area, power, and timing impact.
• Lead post-silicon bring-up and debug on Automated Test Equipment (ATE); root-cause silicon failures and optimize test time.
• Design DFT approaches for low-power, multi-voltage and power-gated designs.

Requirements

Must-have technical skills and tools experience; nice-to-have items listed separately.

• 12+ years DFT experience with leadership responsibility (lead/principal role).
• Proficiency with industry DFT tools such as Synopsys TestMAX, Siemens/Mentor Tessent, Cadence Modus.
• Expertise in MBIST with repair capabilities, scan methodologies, IJTAG (IEEE 1687), and boundary scan (IEEE 1149.1/6).
• Proven experience with FinFET process nodes (7nm, 5nm, or below).
• Experience with ATPG flows (stuck-at, transition, path delay) and scan insertion flows.
• Hands-on experience with post-silicon bring-up and ATE debug.
• Experience designing DFT for low-power/multi-voltage/power-gated architectures.
• Nice-to-have: background in edge systems reliability, IST, POST strategies, or yield-analysis collaboration.

Education Requirements

Bachelor’s degree in a related field.

About the Company

Company: EnCharge AI

EnCharge AI develops advanced AI hardware and software systems for edge-to-cloud computing, focusing on in-memory computing technology to deliver high compute efficiency and density with low power consumption. Founded in 2022, the company targets power-, energy-, and space-constrained applications with integrated hardware architectures and software stacks for scalable, reliable AI deployment.