Lead Designer, Layout

Job Title

Lead Designer, Layout

Role Summary

Execute full-custom analog and mixed-signal IC layouts from floorplan through signoff, developing parasitic-aware layout strategies across multiple product lines.

Lead layout reviews, mentor junior designers, collaborate with circuit design and product teams, and support layout methodology and automation efforts. Position may require up to 10% travel.

Experience Level

Senior - requires 7+ years of custom analog/mixed-signal IC layout experience.

Responsibilities

Deliver production-ready block and chip layouts, ensure signal and power integrity, and improve layout productivity and reliability.

• Execute full-custom layout for analog and mixed-signal blocks including power FET metallization, LDOs, references, gate drivers, charge pumps, signal conditioning, and data converters (SAR, delta-sigma, pipeline ADC, precision DAC).
• Develop block-level and chip-level floorplans optimizing area, routing, power distribution, and signal integrity.
• Apply precision matching techniques: common-centroid, interdigitation, symmetry, shielding, guard rings, and deep N-well isolation.
• Perform physical verification (DRC, LVS, ERC) and parasitic extraction; drive post-layout simulation correlation and optimization with circuit designers.
• Assess electromigration, IR drop, and layout-dependent effects; incorporate DFM and reliability practices including ESD and latch-up prevention.
• Support layout methodology improvements, automation (SKILL, Python/TCL, AI/ML), and mentor junior designers.

Requirements

Core technical skills and proven delivery in full-custom analog/mixed-signal layout.

Must-have

• 7+ years of custom analog/mixed-signal IC layout experience.
• Proficiency with Cadence Virtuoso Layout Suite and physical verification tools (Calibre or Cadence PVS).
• Proven track record delivering layouts through tapeout and production release.
• Experience with precision matching layout for bipolar and MOS transistors, resistors, and capacitor arrays in CMOS and BCD processes.
• Proficiency in parasitic extraction, layout-dependent effects, and post-layout simulation correlation.
• Strong presentation, technical writing, and communication skills.

Nice-to-have

• Experience or strong interest in applying AI/ML to layout automation (generative layout, DRC-aware routing, predictive parasitic estimation).
• SKILL scripting or Python/TCL automation experience to improve layout productivity.
• Familiarity with high-voltage and BCD process layout (DMOS/LDMOS metallization, gate metal strapping, multi-voltage domain isolation).

Education Requirements

Not specified.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.