Lead Design Engineer, SoC / Subsystem / IP

Job Title

Lead Design Engineer, SoC / Subsystem / IP

Role Summary

Lead design and integration of complex SoC, subsystem, and IP blocks from architecture interpretation through RTL delivery and design closure. Own micro-architecture, RTL development, quality reviews, and cross-functional coordination with verification, physical design, DFT, firmware, and architecture teams.

Drive reusable, implementation-ready designs that meet power, performance, and area targets.

Experience Level

Senior — 4 to 18 years of experience; preferred 10–14 years in digital design and SoC/IP development.

Responsibilities

Primary responsibilities include end-to-end RTL design, integration, and delivery of SoC/subsystem/IP blocks.

• Translate architecture and product requirements into detailed micro-architecture and implementation plans.
• Develop and maintain RTL (Verilog/SystemVerilog) focused on correctness, reusability, and scalability.
• Design interconnects, controllers, bridges, memory interfaces, datapaths, and control logic.
• Lead block- and subsystem-level integration; resolve interface, timing, and functional issues.
• Collaborate with verification, physical design, DFT, firmware, and architecture teams on timing, power, area, clocking, reset, synthesis, and closure.
• Support lint, CDC, RDC, synthesis, STA, DFT, low-power, and formal checks and drive closure on issues.
• Analyze and resolve design bugs found in simulation, emulation, silicon bring-up, or customer use cases.
• Mentor junior engineers and provide technical direction on coding practices, design quality, and methodology.
• Contribute to reusable IP development, automation, and design methodology improvements.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Must-have: Significant experience in digital RTL design using Verilog/SystemVerilog and micro-architecture definition.
• Strong understanding of digital design fundamentals: FSMs, pipelines, arbitration, buffering, clock/reset design.
• Experience with AMBA protocols (AXI, AHB, APB) and designing interconnects, bus fabrics, DMA, memory-mapped peripherals, and protocol bridges.
• Proven debugging skills across simulation, synthesis, and integration flows.
• Familiarity with lint, CDC, RDC, synthesis, STA constraints, DFT and low-power design flows; experience with power, performance, and area optimization.
• Scripting for automation (Python, Perl, Tcl, Shell).
• Strong communication and cross-functional collaboration skills; experience leading or mentoring team members.
• Nice-to-have: PCIe, DDR, NoC, cache/coherency, security/safety designs; UPF/CPF low-power methodologies; formal verification support and silicon debug experience.

Education Requirements

Bachelor's or Master's degree (BE/BTech/ME/MTech) in Electronics, Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.