Lead Design Engineer

Job Title

Lead Design Engineer

Role Summary

Lead the functional verification strategy and execution for complex ASIC/SoC blocks, owning verification architecture, coverage, and sign-off criteria. Act as the primary technical liaison between design, architecture, and emulation teams.

The role focuses on creating scalable UVM/SystemVerilog testbenches, driving debug and root-cause analysis, and mentoring junior engineers to ensure timely, high-quality deliverables.

Experience Level

Senior - the posting requests 4–7 years of hands-on design verification (DV) experience in semiconductor/ASIC/SoC environments.

Responsibilities

Accountable for verification planning, execution, and technical leadership throughout the verification lifecycle.

• Define verification strategy and select methodology, tools, and infrastructure (typically UVM/SystemVerilog).
• Design scalable, reusable testbench architectures including BFMs, monitors, scoreboards, and checkers.
• Develop complex test cases and constrained-random sequences to achieve functional coverage goals.
• Lead debug and root-cause analysis; collaborate with design engineers to implement fixes.
• Use formal verification and gate-level simulation where appropriate to find deep bugs and verify timing/reset behavior.
• Monitor and analyze functional and code coverage; define and enforce "definition of done" for verification sign-off.
• Mentor junior engineers on coding standards, verification techniques, and debugging practices.
• Coordinate verification schedules, identify risks, and prioritize tasks to meet project deadlines.

Requirements

Must-have technical skills and experience; nice-to-have items are noted.

• 4–7 years of hands-on design verification experience in semiconductor/ASIC/SoC companies.
• Proven expertise in UVM/SystemVerilog testbench development and constrained-random verification.
• Experience creating BFMs, monitors, scoreboards, checkers, and reusable verification components.
• Strong debug skills and experience performing root-cause analysis with design teams.
• Experience with coverage-driven verification and gate-level simulation workflows.
• Familiarity with formal verification tools and property checking (preferred).
• Demonstrated ability to mentor engineers and lead cross-functional technical discussions.
• Good project management skills: risk identification, timeline management, and prioritization.

Education Requirements

B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or a related field.

We’re doing work that matters: this role contributes directly to ensuring silicon quality and delivery.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.