Lead Design Engineer

Job Title

Lead Design Engineer

Role Summary

Responsible for end-to-end physical implementation and signoff of high-performance interface IPs and testchips at advanced process nodes. Works on floorplanning, power grid design, place & route, clock tree synthesis, timing/SI closure, EM/IR signoff, and physical verification to deliver tapeouts.

Collaborates closely with RTL and analog teams to meet PPA targets and tapeout schedules using Cadence implementation and verification tools.

Experience Level

Senior — typically expects around 4–6 years of hands-on physical design experience.

Responsibilities

Key responsibilities include implementing and closing the physical design flow for advanced IPs and ensuring successful tapeouts.

• Take ownership of floorplanning, power grid design, place & route, clock tree synthesis, and timing/SI closure.
• Perform power (EM/IR) analysis and signoff, and resolve signal integrity and crosstalk issues.
• Execute physical verification (DRC/LVS/antenna) and DFM closure.
• Optimize PPA for interface IPs (e.g., DDR, LPDDR, PCIe, UCIE) and testchips at advanced nodes (7nm/5nm/3nm/2nm).
• Use Cadence backend tools (Genus, Innovus, Tempus, Voltus, Quantus, PVS) for implementation and signoff.
• Work with RTL and analog teams to resolve integration issues and meet tapeout schedules.
• Develop automation to improve flow efficiency and repeatability.

Requirements

Must-have technical skills and experience; a short list of desirable additions follows.

• Proven hands-on experience in physical design and physical verification for ASICs and IPs (hierarchical physical design strategies and deep sub-micron issues).
• Strong knowledge of static timing analysis, low-power design techniques, EM/IR analysis, SI/crosstalk analysis, formal verification, DFT, and physical verification practices.
• Track record of successful tapeouts of complex IPs and SoCs at advanced nodes (examples listed: 16/10/7/5/3 nm).
• Automation and scripting experience (Makefile, Tcl, Perl, Python) and a programming-minded approach to improve flows.
• Excellent communication, analytical and problem-solving skills; self-motivated and collaborative team player.
• Nice-to-have: deep expertise with specific Cadence tools (Quantus, PVS, Voltus) and other backend signoff tools.

Education Requirements

B.Tech / BE / ME / M.Tech in engineering; the role expects approximately 4–6 years of hands-on physical design experience as stated in the posting.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.