Lead Design Engineer

Job Title

Lead Design Engineer

Role Summary

Lead the design, micro-architecture, RTL development, and integration of complex SoC, subsystem, and IP blocks from architecture interpretation through RTL delivery and design closure. Coordinate across verification, physical design, DFT, firmware, and architecture teams to deliver implementation-ready designs that meet power, performance, and area targets.

Experience Level

Senior-level. The posting lists a broad experience range (4–18 years) and specifies 10–14 years of digital design experience in the required skills section.

Responsibilities

Primary ownership of RTL design, micro-architecture, and subsystem integration with a focus on quality and closure.

• Translate architecture and product requirements into detailed micro-architecture and RTL implementation plans.
• Develop and review RTL (Verilog/SystemVerilog) for interconnects, controllers, bridges, memory interfaces, datapaths, and control logic.
• Drive block- and subsystem-level integration; resolve interface, timing, and functionality issues.
• Collaborate with verification, physical design, DFT, and firmware teams to ensure design quality, timing, power, and area goals.
• Support lint, CDC, RDC, synthesis, STA, low-power checks (UPF/CPF), and formal checks as required to achieve signoff.
• Analyze and debug design bugs found in simulation, emulation, silicon bring-up, or customer use cases.
• Mentor junior engineers and provide technical guidance on coding practices, design quality, and methodology.
• Contribute to reusable IP development, methodology improvements, and automation initiatives.

Requirements

Must-have technical skills and domain experience; preferred items listed separately.

• 10–14 years of experience in digital design with significant IP, subsystem, or SoC development exposure.
• Strong RTL design skills in Verilog/SystemVerilog; emphasis on correctness, reusability, and scalability.
• Solid understanding of digital fundamentals: FSMs, pipelines, arbitration, buffering, clock/reset design.
• Experience defining micro-architecture and implementing hardware for interconnects, bus fabrics, DMA, memory-mapped peripherals, and protocol bridges.
• Familiarity with AMBA protocols (AXI, AHB, APB).
• Debugging skills for simulation, synthesis, and integration issues; experience with silicon debug is beneficial.
• Familiarity with lint, CDC, RDC, synthesis, STA constraints, DFT, and low-power design flows; experience optimizing power, performance, and area.
• Scripting experience for automation (Python, Perl, Tcl, or Shell).
• Strong communication and cross-functional collaboration skills.

• Experience with PCIe, DDR, NoC, cache/coherency, security, or safety-related designs.
• Exposure to UPF/CPF low-power methodologies, formal verification support, and silicon bring-up/debug.
• Prior experience leading small design teams or owning major subsystems in large SoC programs.

Education Requirements

Bachelor's or Master’s degree (BE/BTech/ME/MTech) in Electronics, Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.