Lead Customer Engagement Engineer - Liberate

Job Title

Lead Customer Engagement Engineer - Liberate

Role Summary

Responsible for enabling Foundry PDK teams and Foundry Design Service teams to deploy signoff-quality standard cell, IO, and memory libraries using the Cadence Liberate Characterization Suite. Focus areas include library modeling methodology, characterization techfile development, and design-ready reference flow enablement to meet foundry signoff requirements.

This role works closely with foundry modeling, signoff, and design service teams to produce consistent, signoff-capable Liberty models and to integrate those models into implementation and verification flows.

Experience Level

Senior. Specific years of experience not specified in the posting.

Responsibilities

Support foundry PDK and design service teams in developing, validating, and integrating characterization models and library flows for advanced process nodes.

• Develop, validate, and maintain Liberate characterization techfiles for standard cell, IO, and memory libraries.
• Collaborate with foundry teams to define SPICE corners, PVT conditions, and RC assumptions for library signoff.
• Enable generation of signoff-quality Liberty models (NLDM / CCS / CCSP) aligned to foundry requirements.
• Characterize timing, power, leakage, noise, and signal-integrity effects for advanced nodes.
• Support PDK qualification and IP vendor enablement through library quality checks and debugging.
• Work with modeling and signoff teams to ensure consistency between library models and downstream STA, power, and reliability analyses.
• Develop and maintain design reference flows for library integration into implementation and signoff flows.
• Advise on corner selection, modeling trade-offs, and model selection for pre-layout, post-layout, ECO, and signoff stages.
• Help debug timing, power, SI, and convergence issues related to library quality and enable reusable library handoff flows across projects.

Requirements

Must-have technical skills and experience relevant to the role; years and formal qualifications not specified.

• Proven experience with Cadence Liberate Characterization Suite and generating Liberty models (NLDM/CCS/CCSP).
• Experience with SPICE-based characterization, corner/PVT definition, and RC extraction assumptions for signoff.
• Knowledge of standard cell, IO, and memory library characterization and quality checks.
• Familiarity with STA, power analysis, and reliability flows and how library models affect downstream signoff.
• Ability to develop and document design-ready reference flows and to support integration in large SoC projects.
• Strong debugging skills for timing, power, SI, and convergence problems related to library models.

Nice-to-have:

• Experience working directly with foundry PDK teams and IP vendors on advanced nodes.
• Prior work enabling large-scale SoC design flows and automated library handoffs.

Education Requirements

Not specified.