Lead C++ Software Engineer

Job Title

Lead C++ Software Engineer

Role Summary

Join the Cadence Palladium compiler team to design and implement high-performance C++ software that compiles designs for a scalable hardware emulation platform. The role focuses on compiler development, logic optimization, partitioning, routing, and performance engineering for large-scale verification flows.

This is a hands-on technical lead role that involves design, implementation, debugging, and collaboration with hardware and EDA teams.

Experience Level

Senior. Typical background per posting: MS with ~2 years' relevant experience or a PhD in engineering, computer science, or a related technical field.

Responsibilities

Primary responsibilities include:

• Design and implement compiler components and algorithms in C++ for the emulator compiler.
• Optimize logic, perform partitioning and routing for large-scale designs.
• Apply multithreading and distributed computing techniques to improve compile performance.
• Debug complex software using tools such as gdb and profiling utilities.
• Work with build systems and version-control workflows to deliver reliable releases.
• Collaborate with hardware/EDA teams to integrate tools and validate flow correctness.
• Provide technical leadership and mentorship to engineering team members.

Requirements

Must-have technical skills and experience:

• Demonstrated proficiency in C++ and general software development best practices.
• Strong understanding of data structures, algorithms, and databases.
• Experience debugging complex software (gdb or equivalent).
• Familiarity with Linux/Unix development environments.
• Experience with build systems and version-control tools.
• Exposure to electronic design platforms or EDA toolchains.
• Strong problem-solving skills and ability to work on large-scale compile problems.

Nice-to-have:

• Experience with multithreading, distributed computing, or parallel algorithms.
• Previous work on emulation, simulation, or compiler toolchains for hardware verification.

Education Requirements

MS in engineering, computer science, or a related field with ~2 years' experience, or a PhD in engineering, computer science, or a related technical field. The posting also references coursework in hardware description languages such as Verilog, SystemVerilog, or VHDL.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.