Lead ASIC DFT Engineer

Job Title

Lead ASIC DFT Engineer

Role Summary

Lead technical ownership of DFT architecture, implementation, verification, and silicon bring-up for complex ASIC and SoC designs. Work across RTL, verification, physical design, STA, and validation teams to ensure robust testability and resolve post-silicon issues.

Experience Level

Senior — 10+ years of hands-on ASIC DFT experience, with end-to-end ownership of DFT projects.

Responsibilities

Primary duties include architecture, implementation, verification, debug, and mentoring within DFT domain.

• Lead DFT architecture, implementation, verification, and design sign-off for complex ASIC/SoC projects.
• Define and execute scan architecture: scan insertion, chain stitching, and compression for high coverage.
• Integrate, implement, verify, and debug MBIST/LBIST during design and silicon bring-up.
• Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for silicon issues.
• Develop and validate DFT constraints, DFT SDC, and support DFT-specific timing analysis and closure.
• Collaborate with RTL, synthesis, LEC, physical design, STA, and silicon validation teams to resolve integration issues.
• Support ATPG pattern generation, ATPG simulations, test coverage analysis, DRC analysis, and diagnosis/debug.
• Lead integration of JTAG, boundary scan, iJTAG, SSN, and IP-level DFT solutions.
• Mentor junior and mid-level DFT engineers and drive DFT methodology and automation improvements.
• Develop automation and debug scripts using TCL, PERL, or Python to improve flow efficiency.

Requirements

Must-have technical skills and experience required to perform the role effectively; followed by preferred items.

Must-have:

• 10+ years hands-on ASIC DFT experience with end-to-end ownership.
• Solid understanding of DFT fundamentals, fault models, test techniques, and coverage concepts.
• Deep expertise in scan architecture, ATPG, MBIST/LBIST, JTAG, boundary scan, and silicon debug.
• Hands-on experience with major EDA tool flows (Synopsys, Cadence, Siemens/Mentor).
• Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
• Post-silicon debug and silicon bring-up experience on large SoC designs and hierarchical DFT flows.
• Familiarity with RTL design, synthesis flows, logical equivalence checking (LEC), PLLs, and physical design impacts on DFT.
• Scripting/automation skills (TCL, PERL, or Python) for flow automation and debug.
• Strong communication skills and ability to work independently and lead cross-functional debug efforts.

Nice-to-have:

• Experience with SMS, Tessent, or SSN tools.
• Experience with yield learning, diagnosis, and manufacturing test optimization.

Education Requirements

Not specified.

About the Company

Company: ZK Technologies

Semiconductor technology company focused on ASIC/SoC design and design-for-test (DFT) engineering, providing engineering services for DFT architecture, silicon bring-up, and test automation.