Lead ASIC Design Engineer

Job Title

Lead ASIC Design Engineer

Role Summary

Senior hardware engineer responsible for architecture, design, integration, and verification of advanced ASIC and FPGA prototypes for sensing, communications, and navigation systems. Work is within MITRE’s Electronic Systems Development Department on multidisciplinary teams supporting national security and government sponsors.

Role includes hands-on prototype development, leading small teams, and coordinating with fabrication partners, EDA vendors, and third-party IP providers. Position requires on-site presence a minimum of four days per week in Bedford, MA.

Experience Level

Senior - typically requires substantial relevant experience (generally 8+ years of related experience; shorter experience may be acceptable with equivalent senior-level background).

Responsibilities

Primary responsibilities include end-to-end digital design and delivery of ASIC/FPGA prototypes and mentoring project teams.

• Architect and implement highly integrated, low-SWaP-C ASIC and FPGA solutions for embedded systems.
• Lead RTL design, simulation, synthesis, timing closure, and verification activities throughout the design lifecycle.
• Integrate third-party IP and collaborate with semiconductor foundries and EDA tool vendors.
• Drive design-for-test, verification, and prototype bring-up, testing, and demonstration.
• Implement and optimize algorithms in hardware and embedded software.
• Lead project efforts, mentor junior engineers, and interface with sponsors.
• Evaluate and incorporate emerging technologies into next-generation systems.

Requirements

Must-have technical skills, clearance eligibility, and workplace requirements.

• Proven experience with RTL languages (VHDL, Verilog, and/or SystemVerilog) and RTL design flows.
• Hands-on experience with industry EDA tool suites (examples: Cadence, Synopsys, Siemens).
• Experience designing and deploying ASICs on advanced process nodes (experience on <16nm reported).
• Experience integrating complex embedded hardware and third-party IP into system designs.
• Proficiency with scripting and automation tools such as Python, TCL, CMake, or similar.
• Experience leading technical efforts and small engineering teams; strong written and verbal communication skills.
• Familiarity with verification methodologies, synthesis, timing closure, and test strategies.
• Ability to work on-site in Bedford, MA at least four days per week.
• Must be eligible to obtain and maintain a U.S. Top Secret security clearance; U.S. citizenship required to be considered.

Nice-to-have:

• Active Secret or Top Secret clearance.
• Experience with leading-edge nodes (<5nm), DFM workflows, processor interfaces, and transistor-level design concepts.
• Experience with UVM/OVM-based FPGA verification and hardware emulation platforms (Cadence Palladium, Siemens Veloce).

Education Requirements

Typically requires a Bachelor’s degree in electrical engineering, computer engineering, or a related field with significant experience (the posting specifies a common profile of 8+ years of related experience with a Bachelor's, or 6+ years with a Master’s). Related technical fields and equivalent practical experience are acceptable per the posting.

About the Company

Company: MITRE

Headquarters: Bedford, Massachusetts, United States

MITRE is a not-for-profit organization dedicated to solving national challenges in defense, cybersecurity, healthcare, aviation, and more. By partnering with the government, MITRE operates R&D centers that develop innovative solutions for public interest. Known for its culture of innovation, it offers exceptional employee benefits, professional growth opportunities, and diversity initiatives to ensure a fulfilling workplace for its staff.