Lead Application Engineer in Digital and STA

Role Summary

This role involves providing technical support for Cadence's signoff timing analysis solutions, working closely with both Cadence and customer R&D teams.

Experience Level

Mid-level, with approximately 4 to 10 years of experience in digital design flow and timing analysis.

Responsibilities

Key responsibilities include:

• Validate new tool releases through regression testing and enhance current processes.
• Investigate and resolve complex timing issues.
• Write and maintain timing constraints, assist in integrating new STA requirements into tools.
• Support customers in using signoff tools on live projects and improve workflows.

Requirements

The ideal candidate will have:

• Good knowledge of Static Timing Analysis and signoff methodologies.
• Hands-on experience with digital implementation flows and timing optimization.
• Proficiency in UNIX/Linux and scripting languages (C-shell, TCL/TK, Python).
• Exposure to AI/ML techniques for design optimization.
• Degree in Electrical/Electronic Engineering, Microelectronics, or a related field.
• Good communication skills; fluent in English, French is a plus.

Education Requirements

Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.