Lead Application Engineer

Job Title

Lead Application Engineer

Role Summary

Customer-facing engineering role responsible for delivering and optimizing SystemVerilog/UVM verification environments and AI-assisted verification workflows for IP, subsystem, and SoC designs. Acts as technical lead for customer engagements, demonstrations, and verification flow automation.

This role combines hands-on verification engineering, AI-enabled testbench automation, and cross-team collaboration with R&D and product teams to solve complex verification problems.

Experience Level

Senior — typically 5+ years of experience in digital design, functional verification, or EDA application engineering.

Responsibilities

Primary responsibilities include customer engagement, verification environment development, AI-assisted workflow creation, and technical enablement.

• Engage with customers to define verification challenges and identify AI-assisted use cases (testbench/component generation, sequence generation, VIP integration, assertions, coverage, failure triage).
• Design, develop, and optimize SystemVerilog/UVM-based verification environments for IP, subsystem, and SoC verification.
• Create reusable prompts, skills, agents, scripts, and AI-assisted workflows for verification tasks and customer integrations.
• Perform simulation, log and waveform analysis, root-cause debugging, and verification flow automation.
• Conduct technical evaluations, benchmarks, demonstrations, workshops, and customer training.
• Troubleshoot integration issues across UVM, simulation tools, VIPs, and AI components.
• Collaborate with R&D, product engineering, and support teams to address customer requirements and technical issues.
• Produce technical collateral, reference flows, best practices, and documentation for AI-assisted verification.

Requirements

Must-have technical skills and professional abilities required to perform the role; preferred skills listed separately.

• Five or more years of experience in digital design, functional verification, or EDA application engineering.
• Strong hands-on experience with SystemVerilog and UVM; experience developing agents, sequences, scoreboards, functional coverage, and register models.
• Deep understanding of constrained-random and coverage-driven verification methodologies.
• Experience integrating and debugging Verification IP in UVM-based environments.
• Experience with simulation, debug, and coverage analysis; low-power verification experience is valued.
• Strong scripting skills (Python, TCL, shell scripting, or Perl).
• Ability to translate verification challenges into practical, measurable AI-assisted solutions.
• Strong problem-solving, communication, presentation, and customer-engagement skills.
• Nice-to-have: experience with Cadence tools such as Xcelium, Verisium, or VIP; experience applying AI to testbench generation, coverage, debug, or regression analysis.
• Nice-to-have: familiarity with LLM APIs, prompt engineering, RAG, vector databases, agent-based workflows, or tool-calling frameworks; experience deploying AI in cloud or on-prem environments.
• Nice-to-have: familiarity with CPU, interconnect, memory subsystem, low-power/UPF verification, or protocols such as AMBA CHI/AXI/AHB, USB/USB4, LPDDR/HBM, UFS/UniPro/M-PHY, PCI Express, DisplayPort, or eMMC.

Education Requirements

MS degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field is specified.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.