Lead Application Engineer

Job Title

Lead Application Engineer

Role Summary

Customer-facing engineering role focused on verification and AI-assisted verification workflows for IP, subsystem, and SoC designs. The role combines SystemVerilog/UVM expertise, verification flow optimization, and development of reusable AI-enabled tools and scripts to solve customer verification challenges.

Experience Level

Senior — typically 5+ years of relevant experience in digital design, functional verification, or EDA application engineering.

Responsibilities

Work with customers and internal teams to design, demonstrate, and deliver verification and AI-assisted solutions.

• Engage with customers to analyze verification challenges and identify AI-assisted use cases (testbench generation, sequence generation, VIP integration, assertion and coverage generation, failure triage).
• Develop and optimize SystemVerilog/UVM verification environments for IP, subsystem, and SoC projects.
• Create reusable prompts, agents, scripts, and AI-assisted workflows for customer applications.
• Perform technical evaluations, benchmarks, demonstrations, workshops, and customer training.
• Troubleshoot UVM, simulation, AI integration, and verification flow issues; perform log and waveform analysis and root-cause debugging.
• Collaborate with R&D, product engineering, and support teams to address customer technical requirements.
• Produce technical collateral, reference flows, and best-practice guidance.

Requirements

Core must-have skills and experience; preferred items are noted where applicable.

• Must-have: 5+ years of experience in digital design, functional verification, or EDA application engineering.
• Must-have: Strong hands-on experience with SystemVerilog and UVM; experience developing agents, sequences, scoreboards, reference models, functional coverage, and register models.
• Must-have: Understanding of constrained-random and coverage-driven verification methodologies.
• Must-have: Experience integrating and debugging Verification IP in UVM-based environments; experience with simulation, debug, and coverage analysis.
• Must-have: Strong scripting skills (Python, TCL, shell scripting, or Perl).
• Must-have: Ability to convert verification challenges into practical, measurable AI-assisted solutions and to communicate effectively with customers.
• Nice-to-have: Experience with Cadence tools such as Xcelium, Verisium, or VIP.
• Nice-to-have: Experience with low-power verification techniques.

Education Requirements

MS degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (specified in the source). No alternative-equivalent language provided.

Responsibilities (Preferred / Additional)

Additional preferred qualifications and domain knowledge that improve fit for complex SoC engagements.

• Experience architecting reusable UVM environments for complex SoC or subsystem verification.
• Experience applying AI or automation to testbench/sequence generation, coverage, debug, or regression analysis.
• Familiarity with LLM APIs, prompt engineering, RAG, vector databases, agent-based workflows, or tool-calling frameworks.
• Experience deploying AI solutions in cloud or on-premises environments.
• Knowledge of CPU, interconnect, memory subsystem, low-power (UPF) verification.
• Familiarity with one or more protocols: AMBA CHI/AXI/AHB, USB/USB4, LPDDR/HBM, UFS/UniPro/M-PHY, PCI Express, DisplayPort, or eMMC.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.