Lead Analog Layout Design Engineer (SERDES/UCie)

Job Title

Lead Analog Layout Design Engineer (SERDES/UCie)

Role Summary

The Lead Analog Layout Design Engineer provides technical leadership for the PMA custom layout team within a SERDES product organization. The role focuses on layout design and sign-off of high-speed UCIe SERDES IP on advanced process nodes and coordination with global engineering teams.

Experience Level

Senior — minimum 7 years of experience in CMOS SERDES or high-speed I/O IC layout design and development.

Responsibilities

Deliver and lead layout work from block implementation through PHY top-level integration and final verification.

• Design high-speed SERDES layouts for UCIe at data rates up to 64 Gbps on advanced nodes (example: 2nm FinFET CMOS).
• Create high-quality analog/mixed-signal layouts and collaborate closely with circuit designers.
• Perform full back-end flow tasks: floorplanning, detailed layout, and foundry DRC/LVS/PV verification.
• Lead technical decisions for block-to-PHY integration, sign-off and quality assurance.
• Coordinate with global teams across multiple time zones (including US west and east coast).

Requirements

Must-have technical skills and experience; additional preferences listed separately.

• Minimum 7 years in CMOS SERDES or high-speed I/O IC layout design and development.
• Proven experience with SERDES circuit blocks such as driver, receiver, serializer/deserializer, phase interpolator, low-jitter PLLs, high-speed clock distribution, bias/bandgap, and voltage regulators.
• Strong analog/mixed-signal layout skills and experience implementing high-speed, high-accuracy cells and IP.
• Experience across the full custom back-end flow and foundry verification processes.
• Effective communication, problem-solving skills, and ability to work cooperatively in distributed teams.
• Willingness and ability to travel (>10%).

Nice-to-have:

• Experience with Cadence layout and verification tools.
• Experience implementing designs >10 Gbps and on process nodes <16 nm.
• Experience collaborating with EDA R&D teams (Virtuoso, PVS) to improve layout tools and flows.
• Interest in evolving analog/custom layout methodologies.

Education Requirements

BEng, MEng or PhD.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.