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Layout Design Staff Engineer

Synopsys
July 09, 2026
Full-time
On-site
Ottawa, Ontario, Canada
$106,000 - $159,000 CAD yearly
Physical Design Jobs, Level - Senior

Job Title

Layout Design Staff Engineer

Role Summary

Senior-layout engineer on a global team developing high-speed SerDes physical interfaces and supporting analog blocks for advanced SoC IP.

Responsible for producing manufacturable, reliable analog and mixed-signal CMOS layouts, supporting porting across foundries, and ensuring quality through verification and validation.

Experience Level

Senior β€” requires 5+ years of relevant experience in analog and mixed-signal CMOS layout design.

Responsibilities

Primary responsibilities include translating schematics into production-ready layouts and verifying their manufacturability and performance.

  • Design and implement complex analog and mixed-signal CMOS layouts, focusing on high-speed SerDes interfaces.
  • Collaborate with circuit designers to meet performance, power, and area targets.
  • Perform floor planning, layout entry, DRC/LVS and parasitic verification; ensure compliance with foundry rules.
  • Apply techniques to mitigate signal integrity, ESD, and latch-up risks (differential routing, shielding, substrate biasing).
  • Optimize layouts for matching, reliability, and to minimize parasitics (EM, IR drop).
  • Support layout porting across multiple foundry nodes and technology platforms.
  • Document layout methodologies, validation results, and best practices for knowledge sharing.

Requirements

The list below separates must-have skills from desirable additions.

  • Must-have: 5+ years of hands-on analog and mixed-signal CMOS layout experience, including complex ICs and deep submicron technologies.
  • Must-have: Deep understanding of layout effects (matching, proximity, reliability, EM, IR) and practical experience with floor planning and verification flows.
  • Must-have: Strong knowledge of signal integrity and mitigation techniques for high-speed interfaces; practical ESD and latch-up mitigation experience.
  • Nice-to-have: Experience with Synopsys EDA tools and industry-standard layout/verification toolchains.
  • Nice-to-have: Familiarity with UNIX and scripting (Tcl, Python) to automate flows and checks.
  • Professional: Good communication, teamwork, organization, and problem-solving skills.

Education Requirements

Bachelor's or advanced degree in Electrical Engineering or Computer Engineering (or equivalent practical experience) with a strong background in transistor-level design and CMOS technologies.


About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

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Date Posted: 2026-07-07