Layout Design Staff Engineer

Role Summary

As a Layout Design Staff Engineer at Synopsys, you will be part of a dynamic Silicon IP team focused on developing high-performance DDR and HBM PHY IPs. You will lead the development of cutting-edge layout designs, mentor junior engineers, and ensure alignment with customer requirements.

Experience Level

Mid-level, requiring 5+ years of relevant experience in layout design.

Responsibilities

You will be responsible for:

• Leading the development of DDR and HBM layout IPs, setting technical standards.
• Providing expertise in layout creation and technical troubleshooting.
• Mentoring junior engineers and managing project efforts.
• Collaborating with teams on layout requirements and quality assurance.
• Conducting layout reviews to ensure compliance with standards.

Requirements

Must-have skills include:

• BTech/MTech in Electronics, Electrical Engineering, or related field.
• 5+ years of experience in layout design, especially in DDR & HBM PHY IP.
• Deep understanding of submicron effects and floorplan techniques in CMOS, FinFET, GAA technologies (7nm and below).
• Expertise in layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation.
• Strong leadership skills and time management abilities.
• Excellent communication skills, both written and verbal.

Education Requirements

A degree in Electronics, Electrical Engineering, or a related field is expected.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.