Layout Design Sr. Engineer

Role Summary

This role involves developing cutting-edge layouts for DDR, HBM, and UCIe PHY IPs using advanced process technologies. The engineer will work closely with a dynamic team to deliver high-performance silicon IPs.

Experience Level

Mid-level; requires a minimum of 2 years of hands-on experience in layout development and physical verification.

Responsibilities

The key responsibilities include:

• Developing layouts for DDR, HBM, and UCIe PHY IPs.
• Executing layout floor planning, routing, and optimization.
• Performing physical verification checks including DRC, LVS, and ERC.
• Applying deep submicron knowledge for nodes (7nm and below).
• Collaborating with cross-functional teams for seamless integration.
• Generating LEF files and supporting various analyses.
• Contributing to process improvements and advocating best practices.

Requirements

Candidates must meet the following requirements:

• BTech/MTech in Electronics, Electrical, or related field.
• Minimum 2+ years of relevant experience.
• Proficiency in DRC, LVS, ERC checks.
• Understanding of deep submicron effects and layout techniques for CMOS, FinFET, and GAA processes.
• Experience with ESD, latch-up, EMIR analysis, and LEF generation.
• Familiarity with layout tools and methodologies.

Education Requirements

BTech or MTech in Electronics, Electrical, or a related field is required.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.