Layout Design Principal Engineer

Job Title

Layout Design Principal Engineer

Role Summary

Lead analog and mixed-signal layout design for SERDES IP blocks (RX, TX, PLL) across advanced process nodes. Own top-level block layout, optimize for signal integrity and reliability, and collaborate with global layout teams.

Work within the Solutions IP Design Group to deliver portable, production-ready silicon IP that meets foundry and customer requirements. Remote work is optional.

Experience Level

Senior — requires 10+ years of relevant analog/mixed-signal layout experience.

Responsibilities

Primary responsibilities include end-to-end layout execution, verification, and technical leadership.

• Design and own analog/mixed-signal layout for SERDES IP blocks including RX, TX, and PLL subcircuits.
• Optimize layouts for signal integrity: differential routing, clock/data path management, and parasitic control.
• Implement ESD and latch-up mitigation strategies across mixed-signal designs.
• Develop custom digital logic cell layouts and associated routing to meet performance targets.
• Perform physical verification and parasitic extraction using ICV, Calibre, Star-RCXT, and PERC.
• Establish layout standards and best practices; provide technical reviews and mentorship to engineers.
• Support design-for-porting and foundry portability across multiple technology nodes.

Requirements

Must-have technical skills and tools experience. Listed items reflect core requirements; optional skills are noted.

• Must-have: Deep experience with analog and mixed-signal CMOS layout, including matching, shielding, and proximity effects.
• Must-have: Proven SERDES subcircuit layout experience (RX, TX, PLL) and handling critical signal paths and clock distribution.
• Must-have: Experience implementing ESD constraints, electromigration and IR-drop mitigation.
• Must-have: Hands-on use of full-custom layout tools (Custom Compiler or equivalent) and verification flows (ICV, Calibre, Star-RCXT, PERC).
• Must-have: Familiarity with design-for-porting techniques and layout-for-reliability practices.
• Nice-to-have: Experience with Jira/Atlassian or similar project management tools and scripting in TCL, PERL, or similar for automation.
• Nice-to-have: Proficiency with MS Office for documentation and reporting.

Education Requirements

MSEE or BSEE with 10+ years of related analog/mixed-signal layout experience. The posting specifies these degrees and the 10+ years of experience requirement.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.