Junior Physical Design Engineer (CPU)
Intel CorporationJob Title
Junior Physical Design Engineer (CPU)
Role Summary
Work on physical implementation and verification of CPU core or subsystem blocks using advanced process technologies. The role supports RTL-to-GDS implementation tasks and collaborates with RTL designers, verification engineers, and full-chip integration teams.
This position provides hands-on experience under mentorship from senior engineers, focusing on timing, power, and manufacturing-aware design closure for high-performance, power-efficient processors.
Experience Level
Entry-level / Early Career. Target candidates: early-career engineers (typical guidance: B.S. + ~2 years of educational or work experience; M.S. with shorter educational experience as noted).
Responsibilities
Primary responsibilities include execution and support of physical design tasks and related analysis:
- Support physical implementation (synthesis, place & route) for CPU blocks under guidance.
- Perform static timing analysis, power analysis, and design rule compliance checks.
- Assist physical verification (DRC/LVS, formal equivalence, noise and electromigration checks).
- Debug and resolve design issues with mentorship from senior engineers.
- Develop and maintain scripts and automation (TCL, Python or similar).
- Collaborate with RTL, verification, and full-chip integration teams; document design work and flows.
Requirements
Technical must-haves and preferred skills. Education details are listed separately below.
- Must-have: Experience with IC design tools (Synopsys or Cadence) covering logic synthesis, place & route, static timing analysis, and design closure.
- Must-have: Experience in physical verification convergence including static timing and power analysis; familiarity with DRC/LVS, electrical rules, noise and electromigration checks.
- Must-have: Scripting experience (TCL plus at least one other interpreted language such as Python, Perl, or Ruby).
- Must-have: Experience synthesizing digital logic blocks integrated into larger SoCs or IP.
- Nice-to-have: Knowledge of floor-planning, routing techniques, clock distribution and other physical-design best practices.
- Nice-to-have: Experience with RTL-to-GDS methodologies, formal equivalence flows, static timing/noise/reliability verification techniques.
- Nice-to-have: Familiarity with Synopsys Fusion Compiler / ICC2 / PrimeTime or Cadence Genus / Innovus tool suites.
Education Requirements
Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field with approximately 2+ years of educational or work experience; or a Master's degree in a related field with shorter educational experience (as listed by the employer). The posting describes academic degree expectations tied to specified years of experience; no specific certifications are required.
About the Company
Company: Intel Corporation
Headquarters: Santa Clara, California, USA
Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.
