IP Verification Engineer - PCIe Focus

Role Summary

The IP Verification Engineer will contribute to developing and validating cutting-edge FPGA and ASIC technologies focused on PCIe and CXL protocols. This role will involve collaboration with cross-functional teams to achieve successful silicon integration and performance.

Experience Level

We are looking for candidates with a proven background in ASIC verification, specifically at the IP level, along with experience in digital design verification. Familiarity with working in a hybrid team setting and strong analytical skills are essential.

Responsibilities

• Collaborate with design and firmware engineers to understand new features in PCIe and CXL IPs.
• Create comprehensive test plans covering interactions between features, hardware, firmware, and software drivers.
• Develop UVM-based testbenches and verification components such as monitors, scoreboards, and checkers.
• Implement various testing strategies, including directed and random tests.
• Conduct regressions and troubleshoot test failures to maintain high design quality and performance.

Requirements

• Proficient in IP-level ASIC verification with hands-on experience in PCIe, CXL, or Ethernet protocols.
• Expertise in Verilog, System Verilog, and Object-Oriented programming.
• Familiarity with UVM-based verification frameworks.
• Experience with automation in the verification cycle and proficiency in scripting languages such as Python or Perl.
• Strong problem-solving skills and an ability to work independently and collaboratively across multiple sites.

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is required.