IP Verification Engineer - Lead

Job Title

IP Verification Engineer - Lead

Role Summary

Senior verification engineer responsible for pre-silicon functional verification and validation of DDR PHY IP used in SoCs. The role sits within the Memory PHY Group in Central Engineering and focuses on delivering compliant, performant PHY IP for desktop, laptop and other products.

Work includes test-plan creation, testbench architecture, automated validation, pre-silicon debug at IP/subsystem/SOC levels, and cross-functional collaboration with digital, analog, RTL and physical design teams.

Experience Level

Senior — typically 10+ years of relevant industry experience in design verification.

Responsibilities

Core responsibilities include planning, executing and improving IP verification and validation flows.

• Create verification test plans and define testbench architecture for IP-level verification.
• Develop and maintain testbenches, directed and constrained-random tests, and verification environments (OVM/UVM/SystemVerilog).
• Automate validation tasks and verification flows to improve efficiency and repeatability.
• Run simulations (NLP and non-NLP), GLS, and analyze waveform/results to find and debug issues.
• Drive pre-silicon validation at IP, subsystem and SoC level and scope verification activities.
• Collaborate with architects, RTL designers and physical design teams to verify complex architectural and microarchitectural features.
• Maintain and improve functional verification infrastructure and methodology.
• Lead technical reviews, provide guidance to team members, remove roadblocks, and ensure timely issue resolution.

Requirements

Must-have technical skills and experience.

• 10+ years of industry experience in design verification (SystemVerilog and OVM/UVM experience expected).
• Proven experience in verification flow from testplan and testbench architecture to verification closure, functional and code coverage.
• Experience with waveform debug, simulation tools and methodologies (including VCS NLP and non-NLP simulations, GLS).
• Team-leading experience and ability to coordinate with cross-geography teams.
• Strong debugging, problem-solving, and written/verbal communication skills.

Nice-to-have / Preferred

• DDR PHY validation experience and familiarity with DFI/DDR/LPDDR protocols.
• Scripting skills (Python, Perl) and familiarity with version control (Git).
• Exposure to Formal Property Verification and modern development tools (editor/AI-assist tools such as VSCode, GitHub Copilot or similar).

Education Requirements

BS or MS degree is required; the posting specifies a BS or MS degree plus 10+ years of relevant industry experience.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.