IP Release Principal Engineer

Job Title

IP Release Principal Engineer

Role Summary

Senior individual contributor in the IP Subsystem Center of Excellence responsible for qualifying, packaging, and releasing IP subsystems for SoC integrators and external customers. Owns front-end release qualification (RTL static checks, synthesis readiness, DFT enablement) and serves as the primary technical contact for IP delivery issues and escalation.

Experience Level

Senior-level role. Typical guidance: Bachelor’s degree + 10–15 years relevant experience, or Master’s/PhD + 5–10 years, or equivalent professional experience.

Responsibilities

Accountable for IP release quality, technical triage, and cross-functional coordination to ensure IP packages are deliverable and integration-ready.

• Lead RTL static analysis sign-off (Lint, CDC, RDC); review and approve static waivers and ensure documentation in the IP release package.
• Drive synthesis readiness: validate synthesis scripts, SDC constraints, UPF, and representative PPA metrics across EDA tools.
• Ensure DFT readiness: scan insertion readiness, BIST/JTAG support, DFT handoff collateral and liaison with DFT teams to resolve blockers.
• Own and execute the IP delivery checklist at milestones (iRTL, Code Complete, RTLF) and validate release packaging and version control.
• Act as first-line technical support for SoC integration teams: triage integration issues, track bugs/actions (Jira), and provide guidance on RTL, constraints, and methodology.
• Collaborate with SoC teams, PD, F/W, emulation, TFM and methodology groups to align rules, tools, and downstream requirements.
• Maintain release quality dashboards, metrics, and status reporting for IP deliveries.

Requirements

Core technical skills and experience required; items listed as "Preferred" are not strictly mandatory.

• Must-have: Extensive Verilog experience and proven experience with RTL static quality flows (Lint, CDC/RDC).
• Must-have: Hands-on experience validating synthesis flows, SDC constraints, UPF, and ensuring no unconstrained endpoints.
• Must-have: DFT knowledge including scan insertion readiness, boundary scan, and DFT collateral review.
• Must-have: Practical scripting skills (Perl/Python) for automation and flow validation.
• Must-have: Track record of delivering production-quality designs on aggressive schedules and ability to triage complex integration issues.
• Preferred: Domain expertise in SoC architecture, processor cores, memory subsystems, and experience with synthesis, floorplanning, place-and-route at subsystem scale.
• Preferred: Experience with memory generation, Ethernet, security, PCIe/CXL, and working with leading foundries and advanced nodes (2nm/3nm/5nm).

Education Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, or a related field (common guidance: Bachelor’s + 10–15 years). Advanced degrees (Master’s or PhD) in these fields are recognized with reduced experience expectations (Master’s/PhD + 5–10 years). The posting also allows equivalent professional experience in lieu of a formal degree.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.