IP Physical Design Engineer
Marvell TechnologyJob Title
IP Physical Design Engineer
Role Summary
Work on physical design and methodology for next-generation, high-performance processor/ASIC IP targeting server, 5G/6G, and networking applications. The role partners with global RTL, verification, and CAD teams to deliver scalable, high-performance implementations.
Position is based in India (Bangalore or Hyderabad). This role may require eligibility to access export-controlled technology; non-U.S. applicants may be subject to export license review.
Experience Level
Senior — typically 10 to 25 years of progressive experience in back-end physical design and verification, including leadership responsibilities.
Responsibilities
Lead and execute physical design implementation and develop automated methodologies to achieve scalable timing, power, and area targets.
- Architect and lead RTL-to-GDSII implementation flows: synthesis, floorplanning, placement, routing, CTS, and timing closure.
- Develop and deploy physical design methodologies and automation flows for complex chips.
- Provide technical leadership and act as a key advisor across multiple projects to resolve implementation challenges.
- Collaborate with RTL, verification, CAD, and cross-functional teams to optimize design execution.
- Mentor and coach senior and junior engineers to improve team capability and best practices.
- Evaluate and drive adoption of EDA tools and partner with CAD and external vendors on tool qualification.
- Represent the physical design team in strategic technical discussions and contribute to roadmap planning.
Requirements
Key technical skills and experience required for the role.
- 10–25 years of hands-on experience in back-end physical design and verification, including leadership experience.
- Deep expertise in RTL-to-GDSII flows: synthesis, place-and-route, clock tree synthesis, and timing closure.
- Strong experience with static timing analysis tools (e.g., PrimeTime, Tempus) and power/signal integrity tools (e.g., Voltus, RedHawk).
- Proficient in scripting and automation using Python, Perl, Tcl, and Makefile.
- Proven track record developing and deploying physical design methodologies and automation flows.
- Strong communication and collaboration skills with demonstrated ability to mentor engineers and influence cross-functional teams.
- Nice-to-have: experience evaluating EDA tools and working with vendors; experience with leading-edge CMOS nodes and processor/ASIC designs for server or networking applications.
Education Requirements
Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, or a related technical field.
About the Company
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
