IP Micro-architect (RTL) Design Engineer

Job Title

IP Micro-architect (RTL) Design Engineer

Role Summary

Senior technical lead responsible for defining architecture and microarchitecture, implementing RTL, and delivering complex custom Infrastructure IPs for high-performance SoCs. The role works within the Custom IP team and interfaces with verification, physical design, firmware, and SoC integration teams.

Primary focus areas include interconnects, memory subsystems, coherency, and high-speed interface IPs from concept through silicon bring-up.

Experience Level

Senior-level. The posting specifies 8–15 years of experience in SoC/IP architecture, microarchitecture, and RTL design; minimum qualifications list degree-plus-experience combinations (see Education Requirements).

Responsibilities

Deliver architecture and RTL for complex custom IP and lead cross-functional technical activities.

• Drive architecture and microarchitecture definition for Infrastructure IPs, NoC, interconnect fabrics, and memory subsystem IPs.
• Produce detailed microarchitecture specifications: datapath, control logic, packet formats, flow control, ordering and coherency rules, and state machines.
• Lead RTL development and collaborate with verification, physical design, firmware, and SoC integration teams.
• Evaluate and optimize trade-offs across performance, power, area, scalability, latency, and implementation complexity.
• Plan and support verification, debug, emulation, FPGA validation, and silicon bring-up activities.
• Ensure RTL quality via lint, CDC/RDC checks, synthesis practices, and timing closure processes.
• Run design and microarchitecture reviews and make technical decisions across projects.
• Mentor junior engineers and provide technical leadership within the IP development team.

Requirements

Must-have technical skills and experience; degrees summarized separately under Education Requirements.

• 8+ years experience in SoC/IP architecture, microarchitecture, and hands-on RTL design using Verilog/SystemVerilog.
• Proven track record delivering complex custom IPs from concept to production silicon.
• Deep experience with one or more areas: Infrastructure IPs, NoC, interconnect fabrics, memory subsystems, cache coherency, or high-speed interfaces.
• Strong understanding of computer and SoC architecture, digital design methodologies, performance modeling, synchronization and flow control, and high-performance data movement.
• Familiarity with design signoff flows: lint, CDC/RDC, synthesis, and timing closure fundamentals.
• Strong debugging, analytical, and written/verbal communication skills.
• Nice-to-have: building protocol-based IPs end-to-end, ASIC implementation flows, scripting (Python/Perl/Tcl), version control (Git, ClearCase), and post-silicon debug/bring-up experience.

Education Requirements

Bachelor's, Master's, or PhD in Computer Science, Computer Engineering, Electrical/Electronics Engineering, or a related field. Minimum qualifications listed: Bachelor's + 4+ years hardware engineering experience; Master's + 3+ years; PhD + 2+ years. (Degrees and year-based experience alternatives are specified by the employer.)

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.