IP Logic Design Engineer

Job Title

IP Logic Design Engineer

Role Summary

Senior RTL/FPGA engineer responsible for architecture, synthesizable RTL implementation, FPGA toolflow management, timing closure, board bring-up, interface validation, and system-level debug for Altera development kits.

Works across IP, board, firmware, and validation teams to deliver development-kit designs from requirements and schematics through hardware bring-up and production readiness.

Experience Level

Senior - 10+ years professional experience in FPGA RTL design, FPGA implementation, and board bring-up (as specified in the posting).

Responsibilities

Key responsibilities include design, integration, verification, and hardware bring-up for FPGA-based development kits.

• Define FPGA architecture, microarchitecture, block diagrams, interface behavior, register maps, clocking and reset strategies.
• Design, code, integrate, and maintain reusable synthesizable RTL using Verilog/SystemVerilog.
• Map board and system requirements into RTL features, diagnostics, loopbacks, and test modes.
• Manage FPGA project flows (Quartus Prime or equivalent): project setup, constraints, synthesis, fitting, static timing analysis, and timing closure.
• Support board bring-up: FPGA configuration, clock/reset validation, memory initialization, and production-readiness testing.
• Validate interfaces via loopback, protocol traffic, stress and interoperability testing, and corner-case exercises.
• Create RTL testbenches and simulation environments using directed tests, assertions, and coverage techniques.
• Lead technical reviews, mentor engineers, and coordinate cross-functional debug to drive issues to root cause.

Requirements

Must-have technical skills and experience.

• 10+ years of professional experience in FPGA RTL design, FPGA implementation, and board bring-up.
• Proven hands-on experience with Verilog and SystemVerilog for synthesizable RTL.
• Practical experience with Quartus Prime or equivalent FPGA toolflows: synthesis, fitting, timing analysis, constraints, and timing closure.
• Strong digital design fundamentals: FSMs, pipelining, FIFOs, CDC/clock-domain crossing, reset-domain crossing, clock generation and sequencing.
• Demonstrated ability to bring up and debug FPGA-based boards in a lab environment with common lab equipment and debug tools.
• Experience with simulation and verification tools (Questa, ModelSim, lint tools, CDC analysis, assertion-based verification).
• Knowledge of Platform Designer/Qsys, Avalon-MM/AVALON-ST, AMBA AXI, DMA, memory-mapped registers, and streaming data paths.
• Experience with high-speed interfaces and IP (PCIe, Ethernet, DDR4/DDR5/LPDDR, HBM, JESD, FPGA transceivers, QSFP, FMC, USB, UART, I2C, SPI, GPIO).
• Strong analytical, written, verbal, and cross-functional communication skills; experience leading technical reviews and mentoring.

Nice-to-have

• Proficiency with Python and Tcl for build, test, regression, automation, and lab workflows; familiarity with Linux.
• Experience reading schematics and collaborating with board, firmware, IP, and validation engineers.
• Familiarity with Quartus debug facilities (Signal Tap), JTAG, oscilloscopes, logic analyzers, and protocol analyzers.

Education Requirements

Bachelor's or master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related discipline (as stated in the posting).

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.