IP Designer Engineer
Lattice SemiconductorJob Title
IP Designer Engineer
Role Summary
The IP Designer Engineer is responsible for developing Connectivity IP portfolios for Lattice FPGA. This role requires close collaboration with architects to translate specifications into high-speed RTL designs, focusing on performance, power efficiency, and logic utilization.
Experience Level
Mid-level, requires a minimum of 7 years of FPGA IP design experience.
Responsibilities
The responsibilities for this role include:
- Building Connectivity IP portfolios for Lattice FPGA.
- Translating specifications into high-speed RTL design.
- Ensuring optimal performance, power, and logic utilization.
Requirements
The following skills and experiences are required:
- Experience in high-speed SERDES and video protocols (e.g. HDMI, SDI, DisplayPort, MIPI).
- Hands-on experience in FPGA RTL design, logic verification, debugging, and timing closure.
- Programming skills in languages such as C/C++, Perl, TCL, or Python.
- Experience in hardware validation or interoperability testing.
- Experience in soft IP packaging, example design, and testbench development is a plus.
Education Requirements
BS/MS/PhD in Electronics or Computer Engineering is required.
About the Company
Company: Lattice Semiconductor
Headquarters: Portland, Oregon, USA
Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.
