IP Design Verification Engineer

Job Title

IP Design Verification Engineer

Role Summary

Join the Logic Design and Validation team in Design Technology Platforms to develop RTL models and pre-silicon verification for test chips on next-generation processes. The role focuses on building verification environments, driving coverage closure, and integrating IP into SoC-level validation flows.

Experience Level

Mid-level. Typically 3+ years of relevant verification or digital design experience.

Responsibilities

Key responsibilities include:

• Design and maintain scalable UVM-based testbenches and reusable verification IP for block, subsystem, and SoC levels.
• Define and drive verification strategies and comprehensive verification plans to achieve coverage closure.
• Develop and integrate RTL components and validate IPs within SoC architectures.
• Develop power verification methodologies and apply power-aware verification practices.
• Create and apply SystemVerilog Assertions (SVA) to improve coverage and detection of functional issues.
• Debug pre-silicon failures, perform root-cause analysis, and drive issues to closure.
• Collaborate with architecture, physical design, and post-silicon teams to refine verification approaches.
• Incorporate post-silicon learnings into pre-silicon verification improvements and maintain verification documentation.

Requirements

Must-have skills and experience:

• Pre-silicon logic validation experience using SystemVerilog and UVM.
• Digital design experience using Verilog and/or SystemVerilog.
• Hands-on UVM testbench design with emphasis on reusability and scalability.
• Experience with coverage-driven verification methodologies and coverage closure practices.
• Experience writing and using SystemVerilog Assertions (SVA).
• Scripting proficiency for automation (Python, Perl, or TCL).
• Proven end-to-end validation experience and pre-silicon validation closure across multiple projects.

Nice-to-have:

• Mixed-signal IP verification experience (PLL, DDR, SerDes).
• Experience with Unified Power Format (UPF) and power-aware verification.
• Familiarity with synthesizable Verilog/SystemVerilog and industry-standard simulation tools.
• Experience with timing and power convergence tools and methodologies.
• Experience applying AI/ML techniques to verification automation.

Education Requirements

Minimum qualifications specify either: (A) Master’s degree in Electrical Engineering, Computer Engineering, or a STEM-related field plus ≥1 year relevant experience; or (B) Bachelor’s degree in Electrical Engineering, Computer Engineering, or a STEM-related field plus ≥3 years relevant experience. Qualifications may be met via a combination of industry experience, internships, and academic coursework (equivalent practical experience acceptable).

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.