IP Design Verification Engineer

Job Title

IP Design Verification Engineer

Role Summary

The IP Design Verification Engineer is responsible for validating IP blocks—specifically LPDDR5 and DDR5 PHY—for SoC applications, ensuring functional correctness, protocol compliance, and integration readiness.

The role works with architects, RTL developers, physical design, and system teams to define verification strategies, implement testbenches, run RTL and gate-level simulations, and improve verification infrastructure.

Experience Level

Senior-level. Typical experience expectations: 6+ years with a Bachelor's degree, 4+ years with a Master's degree, or 2+ years with a PhD.

Responsibilities

Core responsibilities include developing verification environments, executing comprehensive validation plans, and driving debug and integration of IP.

• Own RTL validation for functional behavior and DFx (design for test/debug).
• Develop OVM/UVM-based testbenches and Bus Functional Models (BFMs) to exercise IP and verify protocol compliance.
• Define verification strategies, methodologies, and detailed test plans.
• Implement and execute test cases, assertions, and functional coverage using SystemVerilog.
• Set up and perform gate-level simulations to verify asynchronous and multi-cycle paths.
• Debug failures in RTL and GLS environments; determine root causes and corrective actions.
• Analyze functional and code coverage metrics to identify verification gaps.
• Automate pre-silicon validation flows by creating scripts or tools.
• Collaborate with system and SoC teams on IP integration and resolve integration issues.
• Maintain and enhance verification methodologies and infrastructure.

Requirements

Must-have technical skills and domain experience; preferred items listed separately.

• Strong proficiency in SystemVerilog and verification methodologies such as OVM and UVM.
• Deep experience with DDR protocols, particularly LPDDR5 and DDR5, across validation stages from spec to coverage.
• Skilled in RTL validation, logic design, DFx concepts, and IP microarchitecture debug techniques.
• Experience with industry verification tools (examples: VCS, DVE, Verdi or equivalents).
• Experience with gate-level simulation setups and debug of asynchronous/multi-cycle paths.
• Familiarity with UNIX environments, shell scripting, and C programming.
• Ability to create automation scripts and tools using languages such as Tcl, Python, Perl, or similar.
• Strong problem-solving and debugging skills for simulation and formal verification issues.

Nice-to-have:

• Proven experience in IP validation across multiple full project lifecycles.
• Experience improving verification efficiency and scaling automated flows.
• Effective written and verbal communication skills for cross-functional collaboration.

Education Requirements

Bachelor's or advanced degree (Master's or PhD) in Electrical Engineering, Computer Engineering, or a related technical discipline. Experience guideline provided in the posting: 6+ years with a Bachelor's, 4+ years with a Master's, or 2+ years with a PhD.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.