IP Design Engineer
Lattice SemiconductorJob Title
IP Design Engineer
Role Summary
The IP Design Engineer will build Connectivity IP portfolios for Lattice FPGA, collaborating closely with architects to translate specifications into high-speed RTL design focused on performance, power, and logic utilization.
Experience Level
Mid-level, requiring a minimum of 3 years of experience in FPGA IP design.
Responsibilities
Key responsibilities include:
- Developing high-speed RTL designs based on specifications.
- Debugging and achieving timing closure for various designs.
- Conducting hardware validation and interoperability testing.
Requirements
Must-have skills include:
- Hands-on experience in FPGA RTL design and logic verification.
- Programming skills in languages such as C/C++, Perl, TCL or Python.
- Familiarity with high-speed SERDES and Video Protocols.
- Experience in soft IP packaging, example design, and testbench development is advantageous.
Education Requirements
A minimum of a BS/MS/PhD in Electronics or Computer Engineering is required.
About the Company
Company: Lattice Semiconductor
Headquarters: Portland, Oregon, USA
Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.
