IP and Subsystem Validation Engineering Manager

Job Title

IP and Subsystem Validation Engineering Manager

Role Summary

Lead and manage validation activities for IP blocks and subsystems within the Data Center Group. Drive verification strategy, implementation of test environments, and presilicon debug to ensure designs meet microarchitectural and functional requirements.

The role involves cross-functional collaboration with architects, RTL developers, and physical design teams to improve verification coverage, deliver complex features, and maintain verification infrastructure.

Experience Level

Senior-level engineering manager. Candidates typically have extensive verification and leadership experience; specific years-of-experience guidance is provided in Education Requirements.

Responsibilities

Primary responsibilities include planning, executing, and improving IP and subsystem verification.

• Develop detailed IP verification plans and implement advanced testbenches and environments.
• Execute verification plans and run system simulations to validate functionality, power, and timing.
• Identify, reproduce, root-cause, and debug issues in presilicon environments; ensure failing tests are resolved.
• Collaborate with architects, RTL developers, and physical design teams to increase verification coverage and enable feature delivery.
• Document verification plans, results, and methodologies; lead technical reviews with internal teams.
• Maintain and enhance functional verification infrastructure, tools, and methodologies for improved efficiency and reliability.
• Define and implement verification infrastructure and test framework methodologies (TFMs) required for design verification.

Requirements

Must-have technical skills and experience for the role.

• Proficiency in RTL design languages and verification (Verilog, SystemVerilog) and Design for Verification (DFV) practices.
• Experience with IP validation tools, test writing, simulation, and debugging techniques in presilicon environments.
• Familiarity with verification methodologies such as Formal Verification, Assertion-Based Verification, and Coverage-Based Verification.
• Strong problem-solving skills with demonstrated ability to isolate and address complex bugs.
• Experience defining and improving verification infrastructure and workflows.

Nice-to-have:

• Leadership experience in technical reviews and mentoring junior engineers.
• Strong technical communication and documentation skills.
• Awareness of industry trends, tools, and methodologies for IP design and verification.

Education Requirements

Degree and experience combinations accepted: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 12+ years of relevant experience; Master's degree with 8+ years; PhD with 6+ years. Equivalent practical experience considered where stated.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.