Intern - Next-Generation HBM Architecture

Job Title

Intern - Next-Generation HBM Architecture

Role Summary

The Memory Systems Architecture team defines next-generation High Bandwidth Memory (HBM) solutions for AI, high-performance computing, and data center platforms. This internship supports architecture and microarchitecture development for future HBM products.

The intern will evaluate memory features, develop performance models and simulators, analyze architectural trade-offs and workload behavior, and collaborate with architects, designers, and cross-functional teams to inform product direction.

Experience Level

Entry-level internship. Suitable for candidates with approximately 0–2 years of relevant experience gained through internships, research, academic projects, publications, or coursework.

Responsibilities

Primary deliverables and day-to-day activities include:

• Research and evaluate next-generation HBM architecture and microarchitecture features (memory scheduling, refresh management, reliability, thermal behavior, controller interactions).
• Develop and extend performance models, simulators, and analytical tools using Python, C++, or similar languages.
• Analyze workload behavior and simulation results to recommend architectural improvements for performance, reliability, and efficiency.
• Use AI-assisted engineering tools and workflows to accelerate software development, data exploration, specification analysis, and documentation while validating outputs with engineering judgment.
• Collaborate with architecture, memory controller, design, and cross-functional teams to support feature definition, design reviews, specifications, and roadmap planning.

Requirements

Must-have technical skills and experience:

• Programming experience with Python and at least one of: C++, SystemVerilog, or a similar engineering language.
• Ability to read and interpret technical specifications, standards documentation, datasheets, and hardware interface definitions.
• Strong analytical and problem-solving skills, plus clear written and verbal communication.
• Experience using AI coding assistants or large language models (e.g., GitHub Copilot, Claude, ChatGPT) as part of engineering workflows.
• Experience analyzing simulation data or developing performance models for hardware or systems.

Nice-to-have (preferred):

• Experience with architectural simulation tools (Ramulator, DRAMSim, gem5, or similar).
• Knowledge of HBM, DDR, LPDDR, GDDR, memory controller architectures, or memory subsystem design.
• Familiarity with memory reliability concepts (ECC, repair mechanisms, refresh algorithms, RAS features).
• Experience with digital design, SystemVerilog, RTL development, or verification methodologies.
• Understanding of AI training/inference accelerator architectures and the role of HBM in large-scale AI systems.

Education Requirements

Currently pursuing a Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. Relevant coursework or project experience in computer architecture, memory hierarchies, DRAM technologies, interconnects, or hardware system design is expected. Internship, research, or academic project experience is acceptable for this internship-level role.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.