Intern in AI System Verification

Job Title

Intern in AI System Verification

Role Summary

Work on a reference integration of PCIe Design IP (DIP) with Accelerated VIP (AVIP) and a hybrid virtual platform to support customer bring-up, debug, and validation of PCIe subsystems. The project spans virtual platforms, RTL integration, simulation/emulation targets, and verification infrastructure.

The intern will collaborate with verification and system-engineering teams to produce a working PCIe DIP + AVIP reference example, improve visibility and debugability, and explore AI-assisted techniques to support bring-up and analysis.

Experience Level

Entry-level internship. Suitable for students or early-career engineers with interest/experience in digital design, verification, or system integration.

Responsibilities

Primary responsibilities and expected deliverables:

• Develop a functional PCIe DIP + AVIP integration example that connects a TLM virtual platform to RTL through AXI/AVIP bridges.
• Enable PCIe enumeration and end-to-end bring-up on a virtual platform and target simulation/emulation environments (Xcelium, Palladium, Protium).
• Create RTL wrappers, glue logic, and verification components needed for integration and automation.
• Provide mechanisms for extracting and visualizing PCIe bring-up/debug information (integration with Verisium Debug and AI debug assistant where applicable).
• Feed PCIe transactions to SystemVIP/SPA for performance monitoring and extract meaningful metrics.
• Document the reference example, test procedures, and recommendations for customer adoption; explore applicability to other high-speed protocols.
• Investigate and prototype AI-based techniques (e.g., assertion generation, connection verification, debug assistants) to improve verification/debug productivity.

Requirements

No explicit mandatory qualifications were listed in the source. The following skills and experience are relevant and will increase impact on this project:

• Hands-on interest or experience with PCIe protocol and system-level integration.
• Familiarity with RTL and verification flows (e.g., SystemVerilog, UVM) and virtual platforms (TLM/SystemC).
• Experience or exposure to AXI interconnects and AVIP/VIP-based integration concepts.
• Exposure to simulation and emulation environments (examples: Xcelium, Palladium, Protium) is beneficial.
• Comfort with Linux, device drivers, or OS-level bring-up concepts for peripheral enumeration is useful.
• Scripting or programming skills (Python, C/C++) for testbench automation and tool integration.
• Nice-to-have: familiarity with debug visualization tools (Verisium), SystemVIP/SPA, and AI/ML techniques applied to verification (Chipstack or similar).

Education Requirements

Not specified.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.