Intern - DRAM Test Structure Design and Layout Engineering

Job Title

Intern - DRAM Test Structure Design and Layout Engineering

Role Summary

Engineering intern on the DRAM Build Enablement and Test Structure Engineering team focused on development, layout, verification, and analysis of semiconductor test structures for advanced DRAM nodes.

This role provides hands-on experience with EDA tools, physical build methodologies, verification flows, and silicon evaluation techniques used in memory technology development.

Experience Level

Entry-level internship. Intended for current students; practical internship experience expectations are minimal and training will be provided.

Responsibilities

Primary duties support design, verification, simulation, and analysis of test structures and related engineering workflows.

• Develop and arrange semiconductor test structures (TEGs) for advanced DRAM nodes.
• Perform physical verification activities including DRC, LVS, and validation checks.
• Run device/process/test-structure simulations to evaluate build assumptions and predict electrical behavior; correlate simulations with silicon data.
• Use layout databases and EDA tools to build, modify, and verify composed layout data.
• Analyze electrical characterization results, generate technical reports, and document findings.
• Write automation scripts (Python, Tcl, etc.) to increase engineering efficiency.
• Explore AI-assisted workflows (including responsible use of LLMs) to support automation, documentation, and analysis.
• Collaborate with technology development, process integration, device engineering, and characterization teams; participate in build reviews and technical discussions.

Requirements

Core technical skills and personal capabilities required or strongly expected for success in the internship.

• Must-have: Basic understanding of semiconductor devices and coordinated circuit fundamentals.
• Experience with coding or scripting languages such as Python, Tcl, or Perl.
• Strong analytical and problem-solving skills.
• Good written and verbal communication skills.
• Nice-to-have: Experience with EDA tools (Cadence Virtuoso, Calibre, or equivalent) and hands-on layout editing experience.
• Familiarity with physical build verification concepts (DRC, LVS) and data analysis/visualization tools.

Education Requirements

Currently pursuing a Bachelor's, Master's, or PhD (or equivalent practical experience) in Electrical Engineering, Computer Engineering, Semiconductor Engineering, Physics, or a related engineering field. Candidates must not graduate prior to September 2027.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.