Intern – DRAM Technology Physical Design and Block-Level PPA Optimization
Micron TechnologyJob Title
Intern – DRAM Technology Physical Design and Block-Level PPA Optimization
Role Summary
The Design Technology Co-Optimization (DTCO) team collaborates across process technology, standard cell architecture, and design implementation to optimize power, performance, and area (PPA) for advanced memory products.
The intern will implement and benchmark standard cell and logic blocks using place-and-route tools and AI-enabled automation techniques, supporting physical design, timing closure, and PPA analysis.
Experience Level
Entry-level (Internship). Expected graduation Fall 2025 or later.
Responsibilities
Work on block-level physical implementation and PPA analysis using industry-standard tools and automation.
- Implement standard cell logic blocks: floorplanning, placement, clock tree synthesis (CTS), routing, and PPA-focused optimization.
- Analyze and benchmark power, performance, and area across standard cell libraries and block configurations to identify improvements.
- Perform static timing analysis (STA), investigate setup/hold violations, and support timing closure activities.
- Execute physical verification checks (DRC, LVS, IR-drop) and assist in resolving design issues.
- Use Generative AI and automation tools to collect data, generate reports, compare results, and streamline PPA workflows.
Requirements
Core technical skills and practical experience required for performing the responsibilities below.
- Must-have: Demonstrated understanding of VLSI design concepts, CMOS circuits, digital logic, and the ASIC physical design flow.
- Practical experience with scripting (Python, Perl, or TCL) via coursework, research, or projects.
- Strong analytical, problem-solving, and debugging skills with attention to technical detail.
- Nice-to-have: Hands-on experience with place-and-route tools (e.g., Synopsys ICC2, Cadence Innovus) and STA tools (e.g., PrimeTime, Tempus).
- Familiarity with design constraints (SDC), LEF/DEF formats, physical implementation methodologies, and low-power standards (UPF/CPF).
- Experience applying AI, Generative AI, LLMs, or AI-assisted automation to engineering workflows.
Education Requirements
Currently pursuing a B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field. Expected graduation Fall 2025 or later.
About the Company
Company: Micron Technology
Headquarters: Boise, Idaho, USA
Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.
