Intern AFG Memoire

Job Title

Intern AFG Memoire

Role Summary

Six-month engineering internship at Cadence France in Sophia-Antipolis within the memory IP / EDA team. The intern will work on SRAM-related research and development, contributing to memory design, characterization, validation, or compiler implementation.

Candidates will be assigned to one of three focused projects: Advanced SRAM Design and Self-Timing Optimization; Statistical Yield Optimization for Next-Generation SRAM Memories; or Power Characterization Methodology for Memory Compilers.

Experience Level

Entry-level (Internship). Intended for final-year engineering students or Master’s students; typically 0–1 years of professional experience. Duration: 6 months, starting early Q1 2027.

Responsibilities

The intern will perform hands-on technical work aligned to one chosen topic. Typical responsibilities include:

• Analyze the impact of process and statistical variations on SRAM behavior, yield, and timing.
• Study and benchmark timing-tracking and self-timing architectures; investigate bitcell-based and hybrid tracking approaches.
• Develop simulation, evaluation, and characterization methodologies for memory circuits and compilers.
• Optimize power characterization strategies and instance selection for memory compilers; validate power trends and interpolation methods.
• Propose, implement and validate architectural or methodology improvements to improve robustness, yield, performance, or power estimation accuracy.
• Perform circuit-level simulations, data analysis, and report results; produce documentation and present findings to engineering teams.

Requirements

Core technical skills and interests expected for successful candidates. Education degree details are in the Education Requirements section below.

• Must-have: Foundational knowledge in CMOS circuit design, SRAM architecture, and basic VLSI concepts; curiosity and problem-solving mindset.
• Experience or coursework with circuit simulation and variability analysis; familiarity with transistor-level tools is beneficial.
• For statistical yield work: interest in statistical analysis and variation-aware design methodologies.
• For power characterization: experience with power analysis, data analysis and scripting (Python, Tcl or Shell preferred).
• Methodical approach, ability to design experiments, and good presentation and reporting skills.
• Nice-to-have: Prior exposure to EDA methodologies, memory compilers, or advanced-node design concepts.

Education Requirements

Final-year engineering student or Master’s student, or equivalent qualification. Relevant fields: microelectronics, electronics, computer engineering, computer science, applied physics, data science, or related technical disciplines; equivalent practical experience accepted.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.