Interconnect Design Engineer

Job Title

Interconnect Design Engineer

Role Summary

Design and deliver configurable interconnect IP, cache controllers, protocol bridges and uncore infrastructure as RTL generators. Work with SoC architects, verification, and software teams to ship high-performance, configurable TileLink-based interconnects for multi-core systems.

Experience Level

Senior-level (senior hardware engineer; no specific years-of-experience listed).

Responsibilities

Key responsibilities include design, integration, and verification of interconnect and uncore IP as configurable generators.

• Architect, design and implement TileLink interconnects, cache controllers, protocol bridges, and other uncore logic as RTL generators.
• Implement self-configuring RTL generator elements that optimally connect to each other.
• Improve multi-core and multi-system coherence and overall performance of interconnects.
• Design extensive configurability into IP and integrate designs into the Chisel/FIRRTL framework.
• Contribute improvements to the framework to enable automated generation of documentation, verification testbenches, and packaged software.
• Perform initial sandbox verification and collaborate with the design verification team on comprehensive verification test plans.
• Create and maintain design documentation and share knowledge within a collaborative engineering culture.

Requirements

Must-have technical skills and attributes.

• Knowledge of cache and cache-coherency architectures and concepts.
• Experience with NoC or other interconnect fabrics.
• Familiarity with industry-standard bus protocols (AXI, AHB, APB, CHI).
• Ability to architect solutions that connect bus fabrics using different protocols (protocol bridges).
• Strong software engineering background: object-oriented and functional programming, templated metaprogramming, compiler/DSL experience, data modeling / intermediate representations, and test-driven development.
• Proficiency in RTL design using Verilog, SystemVerilog, or VHDL.
• Attention to detail, focus on high-quality design, and ability to work effectively in teams.

Nice-to-have:

• Experience with Scala/Chisel, Bluespec, or other DSLs for configurable hardware.
• Knowledge of the RISC-V architecture.
• Experience with Git/GitHub, Jira, and Confluence.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline, or equivalent practical experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.