Integration Design Engineer

Job Title

Integration Design Engineer

Role Summary

Member of Lattice Semiconductor's R&D engineering organization responsible for implementing and integrating custom and digital designs for programmable devices. The role focuses on transistor- and RTL-level implementation, timing and power characterization, and design-for-test flows to support tapeout and silicon validation.

The position is based in Penang, Malaysia, and requires working with cross-functional teams on product development, verification, and silicon bring-up.

Experience Level

Senior — requires significant industry experience; the posting specifies at least 12 years of proven, in-depth experience in custom and digital design implementation.

Responsibilities

Core responsibilities include hands-on design implementation and integration across custom and digital domains, plus engineering coordination for product development.

• Implement and integrate custom transistor-level and digital RTL designs.
• Perform schematic/layout entry and transistor-level analysis using industry tools (e.g., Cadence Virtuoso and SPICE-based characterization).
• Develop and verify RTL, perform synthesis, static timing analysis (STA), and SDC management with industry tool flows.
• Support DFT flow and ATPG generation; collaborate on test insertion and validation.
• Participate in IP and full-chip verification and equivalence checking.
• Write and maintain scripts and automation for flows (Perl, Tcl, Shell, Skill, Python).
• Work with cross-functional teams on planning, resourcing, tapeout, silicon characterization, and product release activities.

Requirements

Must-have technical skills and domain expertise, plus a track record of delivery on complex silicon projects.

• Expertise in Verilog and SystemVerilog for design and verification.
• Deep experience with custom design flow: transistor-level analysis, characterization, and performance/power simulation (SPICE preferred).
• Strong knowledge of digital design flow: RTL coding and verification, linting, elaboration/compilation, synthesis, equivalence checking, SDC, and STA using industry-standard tools (examples: Xcelium, Genus, Innovus, Tempus).
• Experience with DFT flows and ATPG generation.
• Proven scripting ability to automate flows (Perl, Tcl, Shell, Skill, Python).
• Ability to collaborate with verification, CAD, test, and product teams through tapeout and silicon bring-up.
• Authorized to work in Malaysia and able to pass background and reference checks.

Nice to have: FPGA/CPLD design and integration experience, IP and full-chip functional verification experience, and prior project leadership on tapeout and silicon validation.

Education Requirements

BS or MS in Electronics, Computer, or Electrical Engineering.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.