Infra Power Design Verification Staff Engineer

Job Title

Infra Power Design Verification Staff Engineer

Role Summary

Senior verification engineer responsible for developing and executing UVM-based verification for high-speed interconnects and power-aware subsystems within SoC/ASIC projects. Works with RTL designers, architects, and validation teams to ensure functional correctness and coverage closure across block and subsystem levels.

Experience Level

Senior - role expects experienced engineers. Typical experience guidance from the posting: ~6+ years with a Bachelor's, ~5+ years with a Master’s, or ~4+ years with a PhD; preferred candidates often have 8–12+ years of ASIC/SoC verification experience.

Responsibilities

The core responsibilities focus on protocol verification, coverage closure, and subsystem integration.

• Develop and maintain UVM-based verification environments for PCIe, CXL, AXI and related protocols.
• Create and execute verification plans for block- and top-level designs (including CHI).
• Perform functional coverage, assertion-based verification, and regression testing to drive coverage convergence.
• Integrate and validate SMMU and Coresight components in subsystem environments.
• Use third-party VIPs (Synopsys, Mentor) for protocol compliance and simulation.
• Implement and improve scoreboards, agents, monitors, and sequences; support constrained-random testing.
• Collaborate with RTL designers, architects, and validation teams to resolve issues and close verification gaps.
• Contribute to power/performance/cost trade-off considerations during verification and support UPF-aware flows.
• Mentor junior engineers and drive verification methodology improvements; debug RTL and gate-level failures.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Strong proficiency in SystemVerilog and UVM verification methodologies.
• Deep protocol knowledge: PCIe (Gen3–Gen6), CXL (1.1/2.0/3.0), AXI/CHI; familiarity with SMMU/Coresight architectures.
• Experience with Synopsys/Mentor VIPs for PCIe/CXL and AMBA protocols.
• Expertise in assertion-based verification (SVA), coverage-driven testing, and constrained-random verification.
• Proficiency in scripting for automation (Python, Perl, Tcl).
• Familiarity with power-aware verification (UPF) and basic formal verification techniques.
• Proven ability to debug RTL and gate-level simulation failures and drive root-cause resolution.
• Good collaboration and mentoring skills.
• Nice-to-have: experience with peripheral protocols (USB, Ethernet), post-silicon validation, and lab bring-up.

Education Requirements

Degree requirement options listed: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related engineering field (with ~6+ years of relevant hardware engineering experience); OR Master's degree in those fields (with ~5+ years); OR PhD in those fields (with ~4+ years). Preferred candidates may hold a Bachelor's, Master’s, or PhD in Electrical, Electronics, or Computer Engineering. Equivalent practical experience considered per the degree/experience combinations above.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.