Infra Design Verification Sr Lead Engineer

Job Title

Infra Design Verification Sr Lead Engineer

Role Summary

Lead verification engineering for infrastructure IP and subsystems, focusing on high-speed interconnect protocols (PCIe, CXL, AXI, CHI) and subsystem integrations (SMMU, Coresight). The role owns UVM-based verification environments, protocol compliance, coverage closure, and cross-team coordination with RTL designers and architects.

Experience Level

Senior-level. Preferred experience: 3–6 years of ASIC/SoC verification experience; minimum practical experience expectations listed by employer include 1–2+ years depending on degree level.

Responsibilities

Primary responsibilities include design verification, environment development, and cross-team collaboration.

• Develop and maintain UVM-based verification environments for high-speed interconnects (PCIe, CXL, AXI).
• Create and execute verification plans for protocols including PCIe, CXL, AXI, and CHI.
• Perform block-level and top-level verification: functional coverage, assertions, and regression testing.
• Integrate and validate SMMU and Coresight components in subsystem environments.
• Use third-party VIPs for protocol compliance and simulation; implement/enhance scoreboards, agents, monitors, and sequences.
• Drive coverage convergence and assertion-based verification to achieve verification closure.
• Debug failures in RTL and gate-level simulations and work with design/architecture teams to resolve issues.
• Mentor junior engineers and contribute to verification methodology improvements.
• Consider performance, power, and cost during verification activities.

Requirements

Must-have technical skills and tools for this role; preferred items listed separately.

• Strong proficiency in SystemVerilog and UVM verification methodologies.
• Deep protocol knowledge: PCIe Gen3/Gen4/Gen5/Gen6, CXL 1.1/2.0/3.0, AXI/CHI.
• Experience with assertion-based verification (SVA) and coverage-driven testing.
• Familiarity with Synopsys/Mentor VIPs for PCIe/CXL and AMBA protocols.
• Proficiency in scripting for automation: Python, Perl, and/or Tcl.
• Experience with coverage-driven verification, random constraint-based testing, and regression frameworks.
• Knowledge of power-aware verification (UPF), formal verification techniques, and performance/power optimization.
• Experience integrating subsystem components (e.g., SMMU, Coresight) and validating system-level behavior.
• Strong debugging skills at RTL and gate-level simulations.

Nice-to-have:

• Experience with PCIe, USB, Ethernet, or other peripheral protocols.
• Exposure to post-silicon validation and lab bring-up.

Education Requirements

Bachelor's, Master's, or Ph.D. in Computer Science, Electrical/Electronics Engineering, Engineering, or a related technical field; employer also allows equivalent practical experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.