IC/RTL Design Engineer, Front-End Engineer

Job Title

IC/RTL Design Engineer, Front-End Engineer

Role Summary

Design and implement the digital front-end RTL for a high-speed optical ASIC, including datapath elements that connect UCIe and the optical front end. Work from block micro-architecture through clean, timing-aware RTL and block-level verification handoff.

This is a hands-on engineering role requiring close collaboration with architecture, DV, DFT, modelling, and backend teams during design, prototyping, and silicon bring-up.

Experience Level

Mid-level — 3+ years of relevant digital RTL design experience.

Responsibilities

Primary responsibilities include front-end RTL design, verification support, and cross-team integration.

• Develop block-level micro-architecture and contribute to interface and register definitions.
• Design and implement front-end RTL in SystemVerilog: datapath elements, UCIe streaming/RDI adapter, elastic FIFOs, and supporting logic.
• Integrate IP, implement parameterization for configurable blocks, and ensure lint/CDC/RDC cleanliness.
• Write block-level testbenches, sanity checks, and assertions (SVA) prior to DV handoff.
• Apply power- and timing-aware design: clock-gating, pipelining, retiming; collaborate with backend on synthesis and timing closure.
• Bring-up and debug across simulation, emulation, and FPGA prototyping; support DV and silicon bring-up, include DFT/debug hooks.
• Collaborate with architecture, modelling, DV, DFT, and backend teams as blocks progress through the flow.

Requirements

Must-have technical skills and practical experience; preferred items are listed separately.

• 3+ years designing digital RTL in SystemVerilog, delivering blocks from micro-architecture to verification handoff.
• Solid digital design fundamentals: pipelining, FSMs, FIFOs, clock-domain crossing, and streaming/bus interfaces (e.g., AXI).
• Discipline in lint-clean and CDC/RDC-clean RTL practices.
• Power- and timing-aware design experience; familiarity with synthesis and working with backend teams on timing closure.
• Strong debug skills in simulation and experience with scripting (Python, Perl, or TCL).
• Ability to write block-level testbenches and assertions (SVA).

Nice-to-have:

• High-speed datapath or SerDes-adjacent interface experience (UCIe, PCIe/CXL, or similar).
• FEC/coding datapath familiarity (e.g., Reed–Solomon) and gray-code mapping.
• Assertion-based verification experience, UVM block-level testbenches, emulation/FPGA prototyping.
• Exposure to scale-up interconnects, NIC/switch/memory-controller datapaths.
• Low-power (UPF) and DFT (scan) concepts; optical transceiver or CPO experience; advanced-node design (N5/N3/N2).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is expected, or equivalent practical experience.

About the Company

Company: Lumilens

Headquarters: San Jose, CA, USA

Lumilens develops integrated photonics and optical interconnect solutions for high-speed data communication and chip-to-chip interfaces, focusing on optical front-end hardware and co-packaged optics for advanced semiconductor systems.