IC/RTL Design Engineer (Front-End)

Job Title

IC/RTL Design Engineer (Front-End)

Role Summary

Design and implement digital front-end RTL for a high-speed datapath that interfaces between UCIe and the optical front end. Work from micro-architecture through timing-aware RTL implementation and block-level verification handoff.

Hands-on engineering role collaborating with architecture, modelling, DV, DFT, and backend teams to deliver production-quality blocks and support bring-up and silicon debug.

Experience Level

Mid-level — typically requires 3+ years of relevant digital RTL design experience.

Responsibilities

Deliver RTL blocks and supporting logic for the front-end datapath and adapters, and support integration, verification handoff, and bring-up.

• Develop block-level micro-architecture and define interfaces and registers for assigned blocks.
• Design and implement SystemVerilog RTL: datapath elements, UCIe streaming/RDI adapter, elastic FIFOs, and control logic.
• Integrate IP and parameterize blocks for configurability.
• Write lint-clean, CDC/RDC-clean RTL following coding and quality standards.
• Create block-level testbenches, sanity checks, and SVA assertions prior to DV handoff.
• Apply power- and timing-aware design practices: clock-gating, pipelining, retiming; collaborate with backend for timing closure.
• Support bring-up and debug across simulation, emulation/FPGA prototyping, DV, and silicon; include DFT/debug hooks as needed.
• Collaborate cross-functionally with architecture, modelling, DV, DFT, and backend teams throughout the flow.

Requirements

Must-have skills and experience; preferred items listed separately.

• Must-have: 3+ years of digital RTL design in SystemVerilog with blocks taken from micro-architecture to verification handoff.
• Strong digital fundamentals: pipelining, FSMs, FIFOs, clock-domain crossing, and streaming/bus interfaces (e.g., AXI).
• Discipline in lint-clean and CDC/RDC-clean RTL practices.
• Power- and timing-aware design experience; familiarity with synthesis and timing closure processes and working with backend teams.
• Strong debug skills in simulation; scripting experience in Python, Perl, or TCL.
• Preferred / Nice-to-have: high-speed datapath or SerDes-adjacent design experience (UCIe, PCIe/CXL), FEC/coding datapath familiarity, SVA and UVM block-level testbench experience, emulation/FPGA prototyping, scale-up interconnect or NIC/memory-controller datapath exposure, low-power/UPF and DFT (scan) concepts, optical transceiver or CPO experience, advanced-node (N5/N3/N2) design exposure.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or a related technical field — or equivalent practical experience.

About the Company

Company: Lumilens

Headquarters: San Jose, CA, USA

Lumilens develops integrated photonics and optical interconnect solutions for high-speed data communication and chip-to-chip interfaces, focusing on optical front-end hardware and co-packaged optics for advanced semiconductor systems.