IC/RTL Design Engineer

Job Title

IC/RTL Design Engineer

Role Summary

Design and implement the digital front-end RTL for a high-speed optical interconnect chip, including datapath elements that connect UCIe to the optical front end. Work from block micro-architecture through timing-aware RTL implementation and block-level verification handoff, collaborating with architecture, modelling, DV, DFT, and backend teams.

Experience Level

Mid-level — requires approximately 3+ years of hands-on digital RTL design experience.

Responsibilities

Primary responsibilities include front-end RTL design, verification readiness, and cross-team integration.

• Develop block-level micro-architecture and define interfaces and registers for assigned blocks.
• Design and implement front-end RTL in SystemVerilog: datapath elements, UCIe streaming/RDI adapter, elastic FIFOs, and supporting logic.
• Integrate IP and implement parameterization for configurability.
• Produce lint-clean, CDC/RDC-clean RTL that follows coding and quality standards.
• Write block-level testbenches, sanity checks, and SVA assertions prior to DV handoff.
• Apply power- and timing-aware design: clock-gating, pipelining, retiming; coordinate with backend for physical closure.
• Bring-up and debug in simulation, emulation, and FPGA prototyping; support DV and silicon bring-up including DFT/debug hooks.
• Collaborate with architecture, modelling, DV, DFT, and backend teams throughout the design flow.

Requirements

Technical must-haves and useful additional experience.

Must-have:

• 3+ years of digital RTL design using SystemVerilog, taking blocks from micro-architecture to verification handoff.
• Strong digital design fundamentals: pipelining, FSMs, FIFOs, clock-domain crossing, and streaming/bus interfaces (e.g., AXI).
• Discipline with lint and CDC/RDC-clean RTL practices.
• Power- and timing-aware design experience, including synthesis and timing closure workflows with backend teams.
• Strong debug skills in simulation and scripting ability in Python, Perl, or TCL.

Nice-to-have:

• Experience with high-speed datapath or SerDes-adjacent interfaces (UCIe, PCIe, CXL, or similar).
• FEC/coding datapath familiarity (e.g., Reed-Solomon) and gray-code mapping.
• Assertion-based verification (SVA) and familiarity with UVM block-level testbenches; emulation/FPGA prototyping experience.
• Experience with scale-up/scale-out interconnects, NICs, switches, or memory-controller datapaths.
• Low-power (UPF) and DFT (scan) concepts; optical transceiver/CPO or advanced-node (N5/N3/N2) design exposure.

Education Requirements

BS or MS in Electrical or Computer Engineering, or equivalent practical experience.

About the Company

Company: Lumilens

Headquarters: San Jose, CA, USA

Lumilens develops integrated photonics and optical interconnect solutions for high-speed data communication and chip-to-chip interfaces, focusing on optical front-end hardware and co-packaged optics for advanced semiconductor systems.