IC Package Layout Engineer, Staff

Job Title

IC Package Layout Engineer, Staff

Role Summary

Design and deliver advanced IC package and SiP physical layouts for SoC products, driving package selection, structure definition, verification and tape-out. Work cross-functionally with chip, mechanical, thermal and vendor teams to meet mechanical, electrical and manufacturing requirements.

Experience Level

Senior-level. Typical experience expectations range from ~3–5+ years in package/system design or related engineering roles, with preferred candidates having 5+ years and deeper domain expertise.

Responsibilities

Principal responsibilities focus on physical package/layout development, optimization, verification and flow automation.

• Lead package selection and next-generation package structure/configuration optimization.
• Perform package/SiP physical design and layout for SoC and drive design through DV and tape-out.
• Coordinate with multi-functional teams (PD, mechanical, thermal, manufacturing) to optimize electrical, mechanical and thermal performance.
• Define and implement design verification and automation strategies to streamline package design and release flows.
• Optimize package pinout and chip floorplan/bump placement in partnership with BU PD teams.
• Ensure layouts meet SI/PI requirements and participate in package design reviews and DRC/DFM activities.
• Evaluate and develop CAD tools, flows, and methodologies; collaborate with vendors on feature development and issue resolution.

Requirements

Must-have technical skills and domain experience; preferred items listed separately.

• Proven experience in IC package physical design and layout for SoC packages.
• Proficiency with Cadence Advanced Package Designer (APD) and SiP design flows.
• Understanding of IC packaging structures and package-board interactions.
• Familiarity with high-speed IO interfaces and layout constraints (crosstalk mitigation, differential pairs).
• Experience with SI/PI tools and concepts (model extraction, S-parameters, RLGC).
• Ability to collaborate across functions and with external vendors to drive design decisions and resolve issues.
• Experience defining verification and automation strategies for package design flows.

Nice-to-have:

• Familiarity with Cadence Allegro platform (PCB Editor, APD/SiP) and Calibre for DRC/LVS.
• Experience with advanced package types (flip-chip BGA, 2.5D/3D interposer) and substrate manufacturing considerations.
• Knowledge of thermal/materials/assembly processes and failure modes.
• Experience with specific SI/PI tools such as XtractIM, PowerSI, HFSS, Q3D.

Education Requirements

Degree expected: Bachelor's, Master’s or PhD in Electrical Engineering, Mechanical Engineering, Materials Science or related technical field. Qualification examples in the posting: BS with 4+ years, MS with 3+ years, or PhD with 2+ years of relevant package/system design or technology engineering experience; preferred candidates may have 5+ years.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.