IC Layout Engineer – Optical Engine Silicon

Job Title

IC Layout Engineer – Optical Engine Silicon

Role Summary

Responsible for full-custom layout of electronic ICs (EICs) and photonic ICs (PICs) for optical interconnect products. Work across floorplan, parasitic-aware layout, verification, and tapeout, and integrate electronic and photonic dies.

Based in Singapore and working with teams in the US and India; the role interacts with assembly and test supply chain and supports cross-location tapeout activities.

Experience Level

Entry-level / Early career. Expectation: 1–3 years in custom analog, RF, or mixed-signal IC layout with at least one tapeout contribution.

Responsibilities

Deliver layout and verification for assigned analog/mixed-signal and photonic blocks from floorplan through tapeout.

• Own device placement, matching, symmetry, shielding, guard rings, routing, and floorplanning for assigned blocks.
• Perform parasitic-aware layout, run extraction, and iterate with designers on net impact.
• Route high-speed signal paths with attention to impedance, coupling, and return paths; implement passive and electromagnetic structures as directed.
• Run and close DRC, LVS, antenna, and density checks; support electromigration and IR drop analysis.
• Support top-level assembly, chip finishing, and tapeout flow coordination.
• Support PIC layout and integration: waveguide routing, bends, tapers, couplers, grating/edge couplers, and photonic electrode routing.
• Execute photonics-specific verification: curvilinear DRC, waveguide connectivity, LVS for custom photonic cells, and clean GDS stream-out.
• Develop scripts and reusable layout structures to improve team throughput.

Requirements

Must-have technical skills and practical layout experience to perform the responsibilities above.

• Must-have: 1–3 years in custom analog, RF, or mixed-signal IC layout and at least one tapeout contribution.
• Must-have: Strong experience with Cadence Virtuoso (Layout XL, constraint-driven flows).
• Must-have: Practical parasitic awareness and physical verification experience (Calibre or PVS DRC/LVS; parasitic extraction with QRC, StarRC, or equivalent).
• Must-have: Fundamentals in electromigration and IR drop: current density limits, power routing, and relevant checks.
• Must-have: Fundamentals of on-chip electromagnetics: coupling, shielding, and high-speed routing constraints.
• Must-have: Some scripting for layout automation (SKILL, Python, or both).
• Must-have: Willingness to overlap with US and India hours during tapeout crunches.
• Nice-to-have: SiGe BiCMOS layout experience and process-specific passive/isolation practices.
• Nice-to-have: Advanced FinFET CMOS layout at 7nm and below, multi-patterning and coloring experience.
• Nice-to-have: Photonic IC layout exposure, PCell experience (Virtuoso SKILL or Python tools such as gdsfactory, KLayout, IPKISS), and curvilinear-to-grid snapping/fracture knowledge.
• Nice-to-have: Familiarity with silicon photonics components (MZM, ring modulators, Ge photodetectors, thermal phase shifters, fiber coupling) and with 2.5D/3D integration and interposer work.

Education Requirements

Diploma, BS, or MS in Electrical or Electronics Engineering, or equivalent hands-on layout experience (explicitly accepts equivalent practical experience).

About the Company

Company: Lumilens

Headquarters: San Jose, CA, USA

Lumilens develops integrated photonics and optical interconnect solutions for high-speed data communication and chip-to-chip interfaces, focusing on optical front-end hardware and co-packaged optics for advanced semiconductor systems.