IC Design Verification Engineer

Job Title

IC Design Verification Engineer

Role Summary

Verify blocks and subsystems of a first-of-its-kind chiplet by building UVM testbenches, writing tests, driving coverage to closure, and debugging across simulation and emulation. Work on mixed-signal co-simulation, hardware-assisted verification, and signoff activities while collaborating with design, architecture, modeling, firmware, and DFT teams.

Join a startup building photonics infrastructure for next-generation AI systems; this role offers hands-on verification ownership with scope to grow as the product and team mature.

Experience Level

Mid-level — typically requires 3+ years of ASIC/SoC functional verification experience.

Responsibilities

Primary verification responsibilities for assigned blocks and subsystems:

• Develop and extend UVM testbenches (agents, sequences, scoreboards) for blocks and subsystems.
• Write directed and constrained-random tests; develop and drive functional coverage to closure.
• Verify in-house engines against algorithmic golden models, including programmable error injection and error-pattern coverage.
• Integrate and use VIP (e.g., UCIe); run compliance, link-training, loopback, and lane-repair scenarios.
• Run regressions, triage failures, and maintain CI/regression flows.
• Register UVM RAL verification, firmware co-simulation, and MCU boot flows on the MCU subsystem.
• Perform mixed-signal co-simulation — verify digital blocks against behavioral / real-number analog models.
• Support hardware-assisted verification on emulation and FPGA prototyping platforms.
• Participate in gate-level and low-power (UPF) verification activities for signoff.
• Collaborate with design, architecture, modelling, firmware, and DFT teams throughout the flow.

Requirements

Key qualifications and skills. "Must-have" items are listed first; "Nice-to-have" lists common preferred experiences.

• 3+ years of ASIC/SoC functional verification experience.
• Strong UVM/SystemVerilog skills and experience with constrained-random, coverage-driven verification.
• Experience building block/subsystem testbenches and driving functional and code coverage to closure.
• Strong debug skills across simulation; scripting experience in Python, Perl, or TCL.
• Familiarity with regression/CI flows and failure triage.

Nice-to-have:

• High-speed SerDes, PAM4, or FEC/coding verification experience.
• Experience with UCIe, PCIe/CXL, Ethernet, or UALink VIP and compliance testing.
• Mixed-signal verification (Verilog-AMS or SystemVerilog real-number models).
• Hardware-assisted verification experience (emulation like Palladium/Veloce and/or FPGA prototyping like HAPS/Protium).
• Low-power/UPF and gate-level simulation; performance-verification methodology.
• Exposure to NICs, Ethernet/IB switches, cache-coherent fabrics, formal verification for control/interlock logic, or portable stimulus.

Education Requirements

BS or MS in Electrical Engineering or Computer Engineering (or equivalent practical experience).

About the Company

Company: Lumilens

Headquarters: San Jose, CA, USA

Lumilens develops integrated photonics and optical interconnect solutions for high-speed data communication and chip-to-chip interfaces, focusing on optical front-end hardware and co-packaged optics for advanced semiconductor systems.