IC Design Engineer (DFT)

Role Summary

The IC Design Engineer (DFT) will focus on defining DFT architecture and implementing DFT schemes at the chip level. The role encompasses verifying DFT logics and patterns using simulations, performing static timing analysis, and debugging DFT patterns on ATE.

Experience Level

Mid-level with relevant experience in DFT methodologies and tools.

Responsibilities

The responsibilities include:

• Participate in chip level DFT architecture definition.
• Implement DFT schemes, including scan, boundary scan, Mem BIST, and Logic BIST.
• Verify all DFT logics and test patterns with simulation.
• Conduct test modes static timing analysis.
• Participate in ATE bring-up and debug the DFT patterns on ATE.

Requirements

Key qualifications include:

• Good understanding of General DFT methodologies such as BIST, SCAN, JTAG, ATPG, and SSN.
• Familiarity with Mentor/Synopsys DFT flow and tools.
• Experience in developing constraints for synthesis/STA.
• Multi-mode, multi-corner STA experience in 16nm and lower technology nodes.
• Experience in silicon debug, diagnosis, and yield improvement.

Education Requirements

Preferred Degree: MS in Microelectronics or related discipline.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.