IC Design Engineer

Job Title

IC Design Engineer

Role Summary

Design engineer responsible for backend physical implementation of SoC blocks and top-level integration using industry P&R flows. Work includes floor-planning, placement, clock tree synthesis, routing, extraction, physical verification, timing closure and ECOs for advanced process nodes (5nm and below).

Role operates within a multi-functional SoC team and is expected to drive automation, improve turnaround time, and ensure right-first-time silicon delivery.

Experience Level

Mid-level — typical experience: M.S. (EE/CS) with 6+ years or B.S. (EE/CS) with 8+ years of relevant backend/physical design experience.

Responsibilities

Primary responsibilities include physical design implementation, verification, and process improvement:

• Perform block- and chip-level floor-planning, partitioning, placement, CTS, routing and physical verification for SoC designs.
• Execute P&R flows and work toward STA (static timing analysis) closure across the TOP level.
• Implement timing and functional ECOs and manage extraction and physical verification steps.
• Integrate top-down and bottom-up physical design for advanced process nodes (5nm and below).
• Build and adapt automation flows to improve quality and TAT.
• Use EDA tools for P&R, PV, STA and ECO and adapt to internal flows quickly.
• Collaborate across cross-functional and cross-site teams to meet project milestones.

Requirements

Must-have technical skills and competencies:

• Deep understanding of backend digital design and physical design flow (placement, CTS, routing, extraction, verification).
• Proficient in timing constraints and physical constraints for SoC integration.
• Experience with backend EDA tools such as Genus, Innovus, Quantus, Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk, or equivalent Cadence/Synopsys/Mentor toolchains.
• Proficiency in scripting and automation; strong expertise in industry languages (Tcl, Perl) and other programming languages used for flow automation.
• Ability to implement ECOs and drive STA closure; strong analytical skills.
• Demonstrated ability to collaborate and lead by example in multi-site or cross-time-zone environments.

Nice-to-have:

• Experience specifically on 5nm and lower technology node physical design projects.
• Prior experience improving automation and re-usable flow development for P&R and signoff cycles.

Education Requirements

M.S. in Electrical Engineering or Computer Science with 6+ years relevant experience, or B.S. in Electrical Engineering or Computer Science with 8+ years relevant experience.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.